FPGA Mining: What is FPGA Mining in Cryptocurrency ...

Mining software • BTCMiner v1.3.0 - Bitcoin Miner for ZTEX FPGA boards

submitted by btcforumbot to BtcForum [link] [comments]

Effects of ETC moving to SHA3

0xBitcoin might experience some benefits from ETC's recent decision to go to SHA3.
For one thing, if ETC developers turn their minds toward SHA3 GPU mining, it seems likely that they'll be very interested in the optimization work already done by Lt. Tofu and Azlehria on Cosmic and Nabiki. But they may also spot additional optimizations, which could most likely be ported back into our miners!
For another thing, since ETC has a larger community than 0xBitcoin's, it's likely that they have people with very diverse skills. As they turn their minds toward SHA3 on FPGAs, I anticipate they will be choosing FPGA boards and writing software for them that probably will not be very difficult to alter to mine 0xBitcoin! Practically speaking, this may result in a new era of mining where a respectable hash rate can be achieved with much less electricity expense.
Basically, if people with EE or hardware development backgrounds in the ETC community pin down some of the variables involved, like development board, it seems very likely that we will be able to get FPGAs mining 0xBitcoin quickly.
We recently exchanged some nice words with Alex Tsankov. He revealed he is doing work that may allow merge mining ETC and other projects like 0xBitcoin. I don't know how good this will be, but it's hard for me to see how this could be a bad thing. It's really great to have nice words from Alex, because he seems like a very smart dude who is very open to collaboration.
I have joined the ETC Discord (edit: link removed for just-Reddit-things reasons, you'll have no trouble finding it) and will be watching for opportunities to tell people there about our miners if they don't know, and watching for info about their developments on SHA3 miners.
submitted by 0xBrian to 0xbitcoin [link] [comments]

Electroneum Fork 324500

Source: https://www.facebook.com/electroneum/posts/2030562537205714
Hi Everyone!
ALL ELECTRONEUM NODE OWNERS MUST UPDATE THEIR SOFTWARE BY BLOCK 324500 (approx. 36 hours from now – this is an URGENT UPDATE – PLEASE SHARE THIS INFORMATION)
We have an urgent software update below for anyone who runs a full Electroneum Node. If you don’t know what a node is , don’t worry! You won’t need to do anything.
We also have a VERY exciting update about an upcoming listing on a top 10 exchange.
How will I mine Electroneum after this update?
Instant Payment vendor API is open for BETA applicants.How can ETN change the world?
Please note that nothing in this message refers to MOBILE MINING – we are referring to the underlying blockchain miners.
Urgent Electroneum Node / RPC / Command Line Wallet Update
ALL ELECTRONEUM NODE OWNERS MUST UPDATE THEIR SOFTWARE BY BLOCK 324500 (approx. 36 hours from now – this is an URGENT UPDATE – PLEASE SHARE THIS INFORMATION)
https://github.com/electron…/electroneum/releases/…/v2.1.0.0
It’s only been a few short days since I made a video and said “our fork went well! We’re ready for 20m Users!”.
The fork was a great success, from a technical standpoint. Unfortunately, we never got back the number of GPU miners that are needed to ensure our network runs smoothly and has stable block emission. A new phenomenon has emerged where a number of users are mining Electroneum in waves. They come on and then leave after a few hours in a coordinated manner to mine ETN in a completely selfish way. We can’t blame people for maximizing their profit, but we have not built up the amount of “hashing power” that is required to make this impossible and create the stability we need in the network.
This has left us at risk. As such, we have to take urgent action to stabilise our network and protect the Electroneum community.
Coinbene Listing Electroneum & our network stability
We have formally agreed and signed contracts to be listed in July on the AWESOME, top 10, cryptocurrency exchange https://Coinbene.com & https://Coinbene.com.br
Coinbene have 1.5m active users and are a GREAT fit for Electroneum. Their primary markets are Latin America and Asia – which fits perfectly with Electroneum’s customer base. They have seen enormous growth over the last few months and have been very positive about the Electroneum Project.
Whilst this is great news, we will need much more hashing power to ensure we have network stability for our listing on this exchange, so we’ve taken the decision that we can’t wait any longer for GPU miners to return to us and we must run an urgent software update to re-introduce ASIC mining to Electroneum.
This is a very positive move for Electroneum. A great deal of Bitcoin’s trust and appeal is from the enormous hashing power and distribution of miners on the network. Bitcoin & LiteCoin have embraced ASICs and we feel that it is the right thing for Electroneum to do the same.
ASICS are becoming more prevalent, they cost considerably less to run than a GPU rig and use a fraction of the electricity. We are going to encourage more ASIC ownership and take our hashing rate up to (and beyond) the enormous levels of hashing power that we had before the May fork.
There is a further development. The first generation of hardware called an FPGA miner is arriving during 2018 and they make ANTI-ASIC capabilities a thing of the past, as they circumvent the slow delivery time of new ASICs by being re-programmable. If we are ready to embrace these rather than fight them, our network hashing power is increased further and our network stability and security is further enhanced.
Because ASICS run cooler, quieter and use a fraction of GPU rig power, they are suitable for MORE people to run in their homes. If you are interested, a search of “Cryptonight ASIC miner” in Google or Ebay will find the equipment needed to mine Electroneum. You will need to be reasonably technical to achieve this!
Having a stable network is absolutely key to both delivering mass adoption and to ensure we have a great relationship with the great exchanges that we’re already listed with, and to encourage more of the larger exchanges to see Electroneum as a coin that they want on board.
How will I mine Electroneum after this update?
If you are a mobile miner – nothing changes. If you are a GPU or ASIC miner then you’ll need to connect to an Electroneum pool but it is important to note that you will need to change your ALGORITHM. You MUST use the algorithm “Cryptonight” and NOT “Electroneum” or “CryptonightV7”. This will ensure your device works after the update. We will communicate this to all pools, but if you are a member of a mining pool – PLEASE LET THE ADMINS KNOW ABOUT THIS CRITICAL UPDATE. They must update their pool node by block 324500, which is only around 36 hours away.
Instant Payment vendor API is open for BETA applicants
Instant Cryptocurrency Payments via smart phone has always been a critical part of what Electroneum required to achieve mass market adoption. It’s never been done, but 9 short months after our ICO we are excited to announce that we have opened to the doors to vendors who would like to accept payment via Electroneum. The application is to be part of the BETA rollout of instant payment, but will operate on the live blockchain with real ETN!
If you run a business or know someone who does – why not recommend they apply to accept ETN. The Press and Marketing opportunities for the first, in any sector, to accept cryptocurrency are huge! Be part of the instant payment API BETA program by completing this form:
https://docs.google.com/…/1FAIpQLSfKTwWT7W4ltmApZO…/viewform
How can ETN change the world?
Instant payment does far more than allow people to pay for their coffee with crypto instead of their VISA card.
If you’d like to know more about Electroneum’s future I suggest you read a fantastic article that describes its coming role in the world, by fellow director Chris Gorman OBE (Officer of the British Empire – awarded by the Queen of England!): https://www.linkedin.com/…/how-cryptocurrency-enable-financ…
Electroneum has one of the largest of all cryptocurrency communities and it is made up of passionate and amazing people. With your support and world changing things we have coming out over the next few weeks, we can use this update to make our blockchain foundation secure and lead the world in mobile cryptocurrency.
I'm sure you agree that we've been through some challenging times which our team have always dealt with and learned from. The strength and support from our community and many of our goals becoming a reality combined with this blockchain update will give us the perfect foundation to deliver the Electroneum vision that we all share.
Thanks for taking the time to read this long message.
Have a great day everyone,
Richard Ells
Founder, Electroneum.com
submitted by MulatuTesh to Electroneum [link] [comments]

Best $100-$300 FPGA development board in 2018?

Hello, I’ve been trying to decide on a FPGA development board, and have only been able to find posts and Reddit threads from 4-5 years ago. So I wanted to start a new thread and ask about the best “mid-range” FGPA development board in 2018. (Price range $100-$300.)
I started with this Quora answer about FPGA boards, from 2013. The Altera DE1 sounded good. Then I looked through the Terasic DE boards.
Then I found this Reddit thread from 2014, asking about the DE1-SoC vs the Cyclone V GX Starter Kit: https://www.reddit.com/FPGA/comments/1xsk6w/cyclone_v_gx_starter_kit_vs_de1soc_board/‬ (I was also leaning towards the DE1-SoC.)
Anyway, I thought I better ask here, because there are probably some new things to be aware of in 2018.
I’m completely new to FPGAs and VHDL, but I have experience with electronics/microcontrollers/programming. My goal is to start with some basic soft-core processors. I want to get some C / Rust programs compiling and running on my own CPU designs. I also want to play around with different instruction sets, and maybe start experimenting with asynchronous circuits (e.g. clock-less CPUs)
Also I don’t know if this is possible, but I’d like to experiment with ternary computing, or work with analog signals instead of purely digital logic. EDIT: I just realized that you would call those FPAAs, i.e. “analog” instead of “gate”. Would be cool if there was a dev board that also had an FPAA, but no problem if not.
EDIT 2: I also realized why "analog signals on an FPGA" doesn't make any sense, because of how LUTs work. They emulate boolean logic with a lookup table, and the table can only store 0s and 1s. So there's no way to emulate a transistor in an intermediate state. I'll just have play around with some transistors on a breadboard.
UPDATE: I've put together a table with some of the best options:
Board Maker Chip LUTs Price SoC? Features
icoBoard Lattice iCE40-HX8K 7,680 $100 Sort of A very simple FPGA development board that plugs into a Raspberry Pi, so you have a "backup" hard-core CPU that can control networking, etc. Supports a huge range of pmod accessories. You can write a program/circuit so that the Raspberry Pi CPU and the FPGA work together, similar to a SoC. Proprietary bitstream is fully reverse engineered and supported by Project IceStorm, and there is an open-source toolchain that can compile your hardware design to bitstream. Has everything you need to start experimenting with FPGAs.
iCE40-HX8K Breakout Board Lattice iCE40-HX8K-CT256 7,680 $49 No 8 LEDs, 8 switches. Very similar to icoBoard, but no Raspberry Pi or pmod accessories.
iCE40 UltraPlus Lattice iCE40 UltraPlus FPGA 5280 $99 No Chip specs. 4 switchable FPGAs, and a rechargeable battery. Bluetooth module, LCD Display (240 x 240 RGB), RGB LED, microphones, audio output, compass, pressure, gyro, accelerometer.
Go Board Lattice ICE40 HX1K FPGA 1280 $65 No 4 LEDs, 4 buttons, Dual 7-Segment LED Display, VGA, 25 MHz on-board clock, 1 Mb Flash.
snickerdoodle Xilinx Zynq 7010 28K $95 Yes Xilinx Zynq 7-Series SoC - ARM Cortex-A9 processor, and Artix-7 FPGA. 125 IO pins. 1GB DDR2 RAM. Texas Instruments WiLink 8 wireless module for 802.11n Wi-Fi and Bluetooth 4.1. No LEDs or buttons, but easy to wire up your own on a breadboard. If you want to use a baseboard, you'll need a snickerdoodle black ($195) with the pins in the "down" orientation. (E.g. The "breakyBreaky breakout board" ($49) or piSmasher SBC ($195)). The snickerdoodle one only comes with pins in the "up" orientation and doesn't support any baseboards. But you can still plug the jumpers into the pins and wire up things on a breadboard.
numato Mimas A7 Xilinx Artix 7 52K $149 No 2Gb DDR3 RAM. Gigabit Ethernet. HDMI IN/OUT. 100MHz LVDS oscillator. 80 IOs. 7-segment display, LEDs, buttons. (Found in this Reddit thread.)
Ultra96 Xilinx Zynq UltraScale+ ZU3EG 154K $249 Yes Has one of the latest Xilinx SoCs. 2 GB (512M x32) LPDDR4 Memory. Wi-Fi / Bluetooth. Mini DisplayPort. 1x USB 3.0 type Micro-B, 2x USB 3.0 Type A. Audio I/O. Four user-controllable LEDs. No buttons and limited LEDs, but easy to wire up your own on a breadboard
Nexys A7-100T Xilinx Artix 7 15,850 $265 No . 128MiB DDR2 RAM. Ethernet port, PWM audio output, accelerometer, PDM microphone, microphone, etc. 16 switches, 16 LEDs. 7 segment displays. USB HID Host for mice, keyboards and memory sticks.
Zybo Z7-10 Xilinx Zynq 7010 17,600 $199 Yes Xilinx Zynq 7000 SoC (ARM Cortex-A9, 7-series FPGA.) 1 GB DDR3 RAM. A few switches, push buttons, and LEDs. USB and Ethernet. Audio in/out ports. HDMI source + sink with CEC. 8 Total Processor I/O, 40 Total FPGA I/O. Also a faster version for $299 (Zybo Z7-20).
Arty A7 Xilinx Artix 7 15K $119 No 256MB DDR3L. 10/100 Mbps Ethernet. A few switches, buttons, LEDs.
DE10-Standard (specs) Altera Cyclone V 110K $350 Yes Dual-core Cortex-A9 processor. Lots of buttons, LEDs, and other peripherals.
DE10-Nano Altera Cyclone V 110K $130 Yes Same as DE10-Standard, but not as many peripherals, buttons, LEDs, etc.

Winner:

icoBoard ($100). (Buy it here.)
The icoBoard plugs into a Raspberry Pi, so it's similar to having a SoC. The iCE40-HX8K chip comes with 7,680 LUTs (logic elements.) This means that after you learn the basics and create some simple circuits, you'll also have enough logic elements to run the VexRiscv soft-core CPU (the lightweight Murax SoC.)
The icoBoard also supports a huge range of pluggable pmod accessories:
You can pick whatever peripherals you're interested in, and buy some more in the future.
Every FPGA vendor keeps their bitstream format secret. (Here's a Hacker News discussion about it.) The iCE40-HX8K bitstream has been fully reverse engineered by Project IceStorm, and there is an open-source set of tools that can compile Verilog to iCE40 bitstream.
This means that you have the freedom to do some crazy experiments, like:
You don't really have the same freedom to explore these things with Xilinx or Altera FPGAs. (Especially asynchronous circuits.)

Links:

Second Place:

iCE40-HX8K Breakout Board ($49)

Third Place:

numato Mimas A7 ($149).
An excellent development board with a Xilinx Artix 7 FPGA, so you can play with a bigger / faster FPGA and run a full RISC-V soft-core with all the options enabled, and a much higher clock speed. (The iCE40 FPGAs are a bit slow and small.)
Note: I've changed my mind several times as I learned new things. Here's some of my previous thoughts.

What did I buy?

I ordered a iCE40-HX8K Breakout Board to try out the IceStorm open source tooling. (I would have ordered an icoBoard if I had found it earlier.) I also bought a numato Mimas A7 so that I could experiment with the Artix 7 FPGA and Xilinx software (Vivado Design Suite.)

Questions

What can I do with an FPGA? / How many LUTs do I need?

submitted by ndbroadbent to FPGA [link] [comments]

Technical Cryptonight Discussion: What about low-latency RAM (RLDRAM 3, QDR-IV, or HMC) + ASICs?

The Cryptonight algorithm is described as ASIC resistant, in particular because of one feature:
A megabyte of internal memory is almost unacceptable for the modern ASICs. 
EDIT: Each instance of Cryptonight requires 2MB of RAM. Therefore, any Cryptonight multi-processor is required to have 2MB per instance. Since CPUs are incredibly well loaded with RAM (ie: 32MB L3 on Threadripper, 16 L3 on Ryzen, and plenty of L2+L3 on Skylake Servers), it seems unlikely that ASICs would be able to compete well vs CPUs.
In fact, a large number of people seem to be incredibly confident in Cryptonight's ASIC resistance. And indeed, anyone who knows how standard DDR4 works knows that DDR4 is unacceptable for Cryptonight. GDDR5 similarly doesn't look like a very good technology for Cryptonight, focusing on high-bandwidth instead of latency.
Which suggests only an ASIC RAM would be able to handle the 2MB that Cryptonight uses. Solid argument, but it seems to be missing a critical point of analysis from my eyes.
What about "exotic" RAM, like RLDRAM3 ?? Or even QDR-IV?

QDR-IV SRAM

QDR-IV SRAM is absurdly expensive. However, its a good example of "exotic RAM" that is available on the marketplace. I'm focusing on it however because QDR-IV is really simple to describe.
QDR-IV costs roughly $290 for 16Mbit x 18 bits. It is true Static-RAM. 18-bits are for 8-bits per byte + 1 parity bit, because QDR-IV is usually designed for high-speed routers.
QDR-IV has none of the speed or latency issues with DDR4 RAM. There are no "banks", there are no "refreshes", there are no "obliterate the data as you load into sense amplifiers". There's no "auto-charge" as you load the data from the sense-amps back into the capacitors.
Anything that could have caused latency issues is gone. QDR-IV is about as fast as you can get latency-wise. Every clock cycle, you specify an address, and QDR-IV will generate a response every clock cycle. In fact, QDR means "quad data rate" as the SRAM generates 2-reads and 2-writes per clock cycle. There is a slight amount of latency: 8-clock cycles for reads (7.5nanoseconds), and 5-clock cycles for writes (4.6nanoseconds). For those keeping track at home: AMD Zen's L3 cache has a latency of 40 clocks: aka 10nanoseconds at 4GHz
Basically, QDR-IV BEATS the L3 latency of modern CPUs. And we haven't even begun to talk software or ASIC optimizations yet.

CPU inefficiencies for Cryptonight

Now, if that weren't bad enough... CPUs have a few problems with the Cryptonight algorithm.
  1. AMD Zen and Intel Skylake CPUs transfer from L3 -> L2 -> L1 cache. Each of these transfers are in 64-byte chunks. Cryptonight only uses 16 of these bytes. This means that 75% of L3 cache bandwidth is wasted on 48-bytes that would never be used per inner-loop of Cryptonight. An ASIC would transfer only 16-bytes at a time, instantly increasing the RAM's speed by 4-fold.
  2. AES-NI instructions on Ryzen / Threadripper can only be done one-per-core. This means a 16-core Threadripper can at most perform 16 AES encryptions per clock tick. An ASIC can perform as many as you'd like, up to the speed of the RAM.
  3. CPUs waste a ton of energy: there's L1 and L2 caches which do NOTHING in Cryptonight. There are floating-point units, memory controllers, and more. An ASIC which strips things out to only the bare necessities (basically: AES for Cryptonight core) would be way more power efficient, even at ancient 65nm or 90nm designs.

Ideal RAM access pattern

For all yall who are used to DDR4, here's a special trick with QDR-IV or RLDRAM. You can pipeline accesses in QDR-IV or RLDRAM. What does this mean?
First, it should be noted that Cryptonight has the following RAM access pattern:
QDR-IV and RLDRAM3 still have latency involved. Assuming 8-clocks of latency, the naive access pattern would be:
  1. Read
  2. Stall
  3. Stall
  4. Stall
  5. Stall
  6. Stall
  7. Stall
  8. Stall
  9. Stall
  10. Write
  11. Stall
  12. Stall
  13. Stall
  14. Stall
  15. Stall
  16. Stall
  17. Stall
  18. Stall
  19. Read #2
  20. Stall
  21. Stall
  22. Stall
  23. Stall
  24. Stall
  25. Stall
  26. Stall
  27. Stall
  28. Write #2
  29. Stall
  30. Stall
  31. Stall
  32. Stall
  33. Stall
  34. Stall
  35. Stall
  36. Stall
This isn't very efficient: the RAM sits around waiting. Even with "latency reduced" RAM, you can see that the RAM still isn't doing very much. In fact, this is why people thought Cryptonight was safe against ASICs.
But what if we instead ran four instances in parallel? That way, there is always data flowing.
  1. Cryptonight #1 Read
  2. Cryptonight #2 Read
  3. Cryptonight #3 Read
  4. Cryptonight #4 Read
  5. Stall
  6. Stall
  7. Stall
  8. Stall
  9. Stall
  10. Cryptonight #1 Write
  11. Cryptonight #2 Write
  12. Cryptonight #3 Write
  13. Cryptonight #4 Write
  14. Stall
  15. Stall
  16. Stall
  17. Stall
  18. Stall
  19. Cryptonight #1 Read #2
  20. Cryptonight #2 Read #2
  21. Cryptonight #3 Read #2
  22. Cryptonight #4 Read #2
  23. Stall
  24. Stall
  25. Stall
  26. Stall
  27. Stall
  28. Cryptonight #1 Write #2
  29. Cryptonight #2 Write #2
  30. Cryptonight #3 Write #2
  31. Cryptonight #4 Write #2
  32. Stall
  33. Stall
  34. Stall
  35. Stall
  36. Stall
Notice: we're doing 4x the Cryptonight in the same amount of time. Now imagine if the stalls were COMPLETELY gone. DDR4 CANNOT do this. And that's why most people thought ASICs were impossible for Cryptonight.
Unfortunately, RLDRAM3 and QDR-IV can accomplish this kind of pipelining. In fact, that's what they were designed for.

RLDRAM3

As good as QDR-IV RAM is, its way too expensive. RLDRAM3 is almost as fast, but is way more complicated to use and describe. Due to the lower cost of RLDRAM3 however, I'd assume any ASIC for CryptoNight would use RLDRAM3 instead of the simpler QDR-IV. RLDRAM3 32Mbit x36 bits costs $180 at quantities == 1, and would support up to 64-Parallel Cryptonight instances (In contrast, a $800 AMD 1950x Threadripper supports 16 at the best).
Such a design would basically operate at the maximum speed of RLDRAM3. In the case of x36-bit bus and 2133MT/s, we're talking about 2133 / (Burst Length4 x 4 read/writes x 524288 inner loop) == 254 Full Cryptonight Hashes per Second.
254 Hashes per second sounds low, and it is. But we're talking about literally a two-chip design here. 1-chip for RAM, 1-chip for the ASIC/AES stuff. Such a design would consume no more than 5 Watts.
If you were to replicate the ~5W design 60-times, you'd get 15240 Hash/second at 300 Watts.

RLDRAM2

Depending on cost calculations, going cheaper and "making more" might be a better idea. RLDRAM2 is widely available at only $32 per chip at 800 MT/s.
Such a design would theoretically support 800 / 4x4x524288 == 95 Cryptonight Hashes per second.
The scary part: The RLDRAM2 chip there only uses 1W of power. Together, you get 5 Watts again as a reasonable power-estimate. x60 would be 5700 Hashes/second at 300 Watts.
Here's Micron's whitepaper on RLDRAM2: https://www.micron.com/~/media/documents/products/technical-note/dram/tn4902.pdf . RLDRAM3 is the same but denser, faster, and more power efficient.

Hybrid Cube Memory

Hybrid Cube Memory is "stacked RAM" designed for low latency. As far as I can tell, Hybrid Cube memory allows an insane amount of parallelism and pipelining. It'd be the future of an ASIC Cryptonight design. The existence of Hybrid Cube Memory is more about "Generation 2" or later. In effect, it demonstrates that future designs can be lower-power and give higher-speed.

Realistic ASIC Sketch: RLDRAM3 + Parallel Processing

The overall board design would be the ASIC, which would be a simple pipelined AES ASIC that talks with RLDRAM3 ($180) or RLDRAM2 ($30).
Its hard for me to estimate an ASIC's cost without the right tools or design. But a multi-project wafer like MOSIS offers "cheap" access to 14nm and 22nm nodes. Rumor is that this is roughly $100k per run for ~40 dies, suitable for research-and-development. Mass production would require further investments, but mass production at the ~65nm node is rumored to be in the single-digit $$millions or maybe even just 6-figures or so.
So realistically speaking: it'd take ~$10 Million investment + a talented engineer (or team of engineers) who are familiar with RLDRAM3, PCIe 3.0, ASIC design, AES, and Cryptonight to build an ASIC.

TL;DR:

submitted by dragontamer5788 to Monero [link] [comments]

Bitcoin is the fake Skycoin

Satoshi Nakamoto said that biggest flaw in Bitcoin network are miners. That's because consensus algorithm, TX hash rate is dependent on miners calculation. Basically, we are consuming a lot of electricity to gather multiple tx in a block, in order to 3 Chinese mining pools can smash that block and take the Bitcoin reward. And if is not enough, the mining pools can inject fake tx in the network to clog it, so TX fees for us (peasants) will go higher.
  1. Why we are using hardware and electricity to create one block?
  2. Why Consensus algorithm is dependent on a new block creation?
  3. Where is the new Internet we all wanted back in 2009-2010 where millions of computer would be the network ?
https://medium.com/@Skycoinproject/cyberbalkanization-and-the-future-of-the-internets-f03f2b590c39
A) Skycoin is the bigger brother of Bitcoin. Early developers of Bitcoin knew that Miners will control the Bitcoin network in the future, so a part of them started to research a new Consensus Algorithm called Obeliskhttps://www.skycoin.net/blog/posts/obelisk-the-skycoin-consensus-algorithm/
B) Skycoin resolved 51% attack, sybil attack, has 0 TX fee, 1-2 sec for a tx , and is private. But the most important thing.
Skycoin is the only crypto out there who fixed the problem of volatility of a cryptocurrency. What's that ? Imagine if price of Skycoin goes higher and higher, peasants will ''HoDL'' it, so the term ''currency '' is lost. Why someone would spend an asset that goes higher and higher?
B1) One Skycoin kept in the wallet is creating non-stop a second currency called CoinHour. 1SKY is creating 24 CoinHours per day and so on. Coinhour is backed by bandwidth => Skywire(Software Defined Network) is the New Internet that gives Skycoin a real value, a commodity level value. https://www.youtube.com/watch?v=-CbSdVIwr8E
B2) In this ecosystem Skycoin behaves like an equity and CoinHour is the real currency. For example Skycoin Price can reach 1 million and the price of Coinhour is independent, its equilibrium is reached by supply and demand of the market https://explorer.skycoin.net/app/blocks/1
C) Ethereum has a buggy prog language and all shitcoins are on Ethereum Blockchain (Database) with only 30 tx/s. Why would someone would gather all the data on ONE Database?!
C1) Skycoin created CX ( first deterministic cryptographic prog language) https://www.skycoin.net/blog/posts/cx-overview/
C2) Skycoin created Fiber https://www.skycoin.net/fibe ( basically you can create your own blockchain with 300-3000 tx/s, private or public , with hardware customization ( law firms, government entities and so on as early adopters)
D) Skywire is the New Internet built at the Hardware and Software level
-Skywire is hardware agnostic
-Skywire has its DYI Antennas
- Skywire has FPGA boards
-Skyiwire has 10k nodes online ( more than TOR)
Bibliography:
  1. https://www.youtube.com/channel/UCMAS-n0SGseIZPxWuaQVFkg
  2. https://www.skycoin.net/downloads/
  3. https://www.skycoin.net/blog/

TLDR: one neighbor is rendering a movie. He wants 1 TB/ s. He will pay CoinHour to his neighbors to borrow bandwidth capacity of their sky clusters and antennas.
Skycoin Address : 25139AGYjwGwgKMZEA268GbJyXrZGWF533i
submitted by CaptainCuc to CryptoCurrency [link] [comments]

Cryptocurrency Mining History : Journey to PoC

Cryptocurrency just like any other technological development has given birth to many side industries and trends like ICO, white paper writing, and mining etc… just the cryptocurrency itself rises, falls and changes to adapt real life conditions, so does its side industries and trends. Today we are going to be focusing on mining. How it has risen, fell and adapted through the journey of cryptocurrency till date.
Without going into details crypto mining is the process by which new blocks are validated and added to the blockchain. It first took to main stream in January 2009 when the mysterious Satoshi Nakamoto launched the bitcoin white paper within which he/she/they proposed the first mining consensus mechanism called proof of work (Pow).
The PoW consensus mechanism required that one should spend a certain amount of computational power to solve a cryptographic problem (nounce) in other to have the have the right to pack/verify the next block on the blockchain. In this mechanism, the more computational power one possesses the more rights they have over the packing of the next block. The quest for faster hardware has seen significant changes in the types of hard ware dominating the PoW mining community.
Back in 2009 when bitcoin first started a normal pc and its processing power worked just fine. In fact a pc with an i7 Intel processor could mine up to 50btc per day but back then it almost nothing since btc was only some few cents. When the difficulty of the network became significantly high, simple computer processing units could not match the competitiveness and so miners settled for something more powerful, the high end graphic processors (GPU). This is when the era of rigs began It was in 2010. People would combine GPUs together in mining rigs on a mother board usually in order of 6 per rig some miners operated farms containing many of these rigs. Of course with greater power came greater network difficulty and so the search for faster hard ware let to implementation of Field Programmable Gate Arrays (FPGA) in June 2012. A further search for faster, less consuming and cheaper hard ware let us to where we are today. In the year 2013, Application Specific Integrated Circuits (ASIC) miners were introduced. One ASIC miner processes 1500H/s which is 100 times processing power of CPU and GPU. But all this speed and efficiency achievements brought about another problem one which touches the core of cryptocurrency itself. The idea of decentralization was gradually fading away as wealthy and big companies are the once who could afford and build the miners therefore centralizing mining around the rich, there was a called for ASIC resistant consensus mechanism.
A movement for ASIC resistant PoW algorithms began the idea is to make ASIC mining impossible or at least make it such that using ASIC doesn’t give a miner any additional advantage as to using CPU . In 2013 the MONERO the famous privacy coin proposed CryptoNight an ASIC resistant PoW consensus at least that is how they intended it to be. But things have proven much more difficult in practice than they had anticipated as ASIC producers keep matching up to every barrier put in place the PoW designers at a rate faster than it takes to build these barriers. MONERO for example has to fork every now and then in other to keep the CryptoNight ASIC resistant a trick which is still not working as reported by their CEO “We [also] saw that this was very unsustainable. … It takes a lot to keep [hard forking] again and again for one. For two, it may decentralize mining but it centralizes in another area. It centralizes on the developers because now there’s a lot of trust in developers to keep hard forking.” Another PoW ASIC resistance algorithm is the RamdonX and there are many others but could quickly imagine that the barriers to ASIC mining in these ASIC resistance algorithm would eventually be broken by the ASIC miners and so a total shift from PoW mining to other consensus mechanisms which are ASIC resistance from core were proposed some of which are in use today.
Entered the Proof of Stake (PoS) consensus mechanism. PoS was first introduced in 2013 by the PeerCoin team. Here, a validator’s right to mine is proportionate to his/heit economic value in the network simple put the more amounts of coins you have the more mining rights you get. Apart from PeerCoin, NEO and LISK also use POS and soon to follow is EThereum. There are different variations to PoS including but not limited to delegated proof of stake DPoS, masternode proof of stake MPoS each of which seek to improve on something in the POS. This is a very good ASIC resistance consensus mechanism but it still doesn’t solves the centralization problem as the rich always have the power to more coins and have more mining rights plus it is also expensive to start. And then we have gotten many other proposals to combat this among which are Proof of Weight (PoW) and Proof of Capacity (PoC). We take more interest in PoC it is the latest and gives the best solution to all our mining challenges consensus as of now.
Proof of Capacity was first was described 2013 in the Proofs of Space paper by Dziembowski, Faust, Kolmogorov and Pietrzak and it is now being used in Burst. The main factor that separates all the mining mechanisms is the resource used. These resources which miners spend in other to have mining rights is a measure of ensuring that one has expense a none-trivial amount of effort in making a statement. The resource being spent in PoC is disk space. This is less expensive since many people already have some unused space lying around and space is a cheap resource in the field of tech. it has no discrimination over topography… it really solves lots of centralized problems present in all most other consensus. If the future is now then one could say the future of crypto mining is PoC.
submitted by seekchain to u/seekchain [link] [comments]

Why is getting into FPGA's such a crappy experience?

I'm a hobbyist and this is my first venture into FPGA's. I understand how FPGA works in theory. It's just a bunch of combinational logic connected by clock-connected flip-flops, whose topology and combinational functions can be programmed with a high level language. I bought a Xilinx board from embeddedmicro.com and I'm going to work through their tutorials.
All I want to be able to do is specify a bunch of like registers and crap, and how to connect them with clocked flip-flops to do some really basic stuff like a simple CPU with 1-2 custom instructions or something. So why do I have to download a GIANT SIX GIGABYTE FILE TO DO THAT? What could this software possibly be doing that it needs to be that big?
In a sane world, all I'd need is a board and a simple compiler which just takes the high-level language and turns it into the topology file to upload to the board. But in the insanity in which I am currently living, I have to download some gigantic IDE that is going to be huge and probably slower than mining bitcoins on an NES. I don't know because IT'S STILL DOWNLOADING.
So to even get to the download, I had to log into the website, register, and give them a name and a physical address (and God forbid I should leave the "Company" field empty!). The Licensing crap on their website looks like you need an MBA to understand it. This company sells pieces of hardware, FFS! Why in Stallman's name can't they just make the software FOSS and let anyone download it instead of all this BS about WEBPACK this and annual upgrade that?
Xilinx, in case you haven't noticed, in order for anyone to actually use your software, THEY HAVE TO BUY A CHIP OR BOARD AND YOU CAN MAKE MONEY OFF YOUR CUSTOMERS THAT WAY. CHARGING FOR SOFTWARE OR HAVING A BYZANTINE PROCESS FOR GETTING A FREE LICENSE MAKES ZERO SENSE FOR A HARDWARE COMPANY.
Anyone know a place where you can just buy an FPGA board, plug it into a USB port, sudo apt-get install some FOSS compiler, type your Verilog or VHDL or whatever into emacs, run 2-5 commands and have a running design?
If such a place doesn't exist, some startup needs to disrupt this industry. If you make it easy for people to develop for your HW, those devs will be inclined buy your product just to make their lives easier.
submitted by white_nerdy to FPGA [link] [comments]

Waltonchain All-in-One - Extended

Welcome!

I would like to warmly welcome everyone to waltonchain
This is an updated, extended community-written post and I will try to update it regularly over time.
Please respect our rules (see sidebar) and feel free to comment, contribute and ask questions.
Don’t forget to subscribe to the subreddit for any news on Waltonchain!
 

Getting Started

What is Waltonchain?

The Waltonchain Foundation is building a cross-industry, cross-data sharing platform by integrating Blockchain with the Internet of Things through self-developed RFID Chips with intellectual property rights.
The in-house developed Waltonchain RFID chips integrate a proprietary, genuine random number generator and an asymmetric encryption logic and hardware signature circuit, all of which are patent-protected.
The combination of self-developed RFID chips and the Waltonchain blockchain will ultimately achieve the interconnection of all things and create a genuine, believable, traceable businessmodel with totally shared data and transparent information.
Waltonchain will unfold a new era of the Value Internet of Things (VIoT).
 
Waltonchain Introduction Video
Launch of Waltonchain
 

The Project

The Waltonchain team has formulated a 4-phase development plan, starting from infrastructure platform establishment to gradually incorporating retail, logistics and product manufacturing, and to finally achieving the full coverage of the business ecosystem.
 
As for the phase 1.0 of the project, the team has developed the clothing system integration scheme based on RFID. The application scenarios at phase 1.0 will establish Golden demonstration template
At phase 2.0, our RFID beacon chip will be massproduced and can be used in clothing, B2C retail and logistics.
At phase 3.0, manufacturers will achieve traceable customization of intelligent packaging.
At the project phase 4.0, with the upgrading and iteration of assets information collection hardware and improvement of blockchain data structure, all assets can be registered in Waltonchain in the future.
 
Original Roadmap Thread

Project-Updates:

Video: WTC-Garment System by Waltonchain & Kaltendin
Video: WTC-Food System by Waltonchain
 

Official Resources

Waltonchain Whitepaper
Waltonchain Official Website
Waltonchain Github
 
Official Official Medium
Official Slack
Official Instagram
Official Facebook
Official Twitter @waltonchain
Official Telegram @waltonchain_en
 
Dedicated community Telegram channel for Waltonchain miners, MN & GMN holders.
@WaltonchainMining
 
 
Chinese Community
本群为沃尔顿链华文官方社群
Chinese Telegram @waltonchain_cn
官方网站 - Waltonchain China - Website
 
Korean Community
공식사이트 - Waltonchain Korea - Website
카카오톡 - Waltonchain Korea - Kakao
트위터 - Waltonchain Korea - Twitter
블로그 - Waltonchain Korea - Naver Blog
인스타그램 - Waltonchain Korea - Instagram
Freyr 공식텔레그램방(한국) - Freyrchain Korea - Telegram
Communities in Progress
Russian Twitter @waltonchain_ru
Russian Website
Japanese Twitter @waltonchain_jp
Japanese Website
Brazilian Twitter @waltonchain_br
 

Waltonchain Wallet

Please note that before the token swap,
DO NOT transfer your ERC20 WTC tokens to the WTC wallet!!
 
Wallet for PC (Github)
Web Wallet - Instruction Manual
Windows Wallet - User Manual
Windows Wallet - Tutorial Video
Wallet for Android
Google Playstore
Github
Android User Manual
Android Wallet - Tutorial Video
 
Wallet for IOS
(pending Apple Store approval)
 
Explorer
Waltonchain Explorer
Waltonchain Blockchain Explorer User Manual
 
Mining
Waltonchain GPU Mining User Manual
Waltonchain Progressive Mining Reward Program
 
Unofficial
Unofficial Guardian Masternode Tracker
waltonchain.tech - Unofficial collection of news and useful resources

The Foundation

>> Waltonchain Organizational Chart <<<--
 
Waltonchain Foundation Ltd. (Singapore) - 沃尔顿链
Waltonchain (HK) Development Co. Ltd. (Head company)
Walton Chain Technology Co. Ltd. (Korea)
Silicon (Shenzhen) Electronic Technology Co. Ltd.
Silicon (Xiamen) Electronic Technology Co.Ltd. (RFID Chip Research)
Silicon (Quanzhou) Electronic Technology Co. Ltd.(IoT Intelligent Switch Chip)
Nanjing Sleewa Information Technology Co. Ltd. (Blockchain)
Quanzhou KEDIHENG Electronic Technology Co. Ltd
Xiamen IOT Technology Co. Ltd.
Xiamen Citylink Technology Co.Ltd.
Xiamen ZhongChuan IOT Industry Research Institute Co.Ltd.
 

The Team

Founder:

Do Sanghyuk (都相爀) – Initiator in Korea
Korean, Vice Chairman of the China - Korea Cultural Exchange Development Committee, Director of the Korea Standard Products Association, Chairman of Seongnam Branch of the Korea Small and Medium Enterprises Committee, Chairman of Korea NC Technology Co., Ltd., Senior Reporter of IT TODAY News, Senior Reporter of NEWS PAPER Economic Department, Director of ET NEWS.
 
Xu Fangcheng (许芳呈) – Initiator in China
Chinese, majored in Business Management, former Director for Supply Chain Management of Septwolves Group Ltd., has rich practical experience in supply chain management and purchasing process management. Currently, he is the Director of Shenzhen Silicon, the Director of Xiamen Silicon and the Board Chairman of Quanzhou Silicon. He is also one of our Angel investors.
 

Senior Experts:

Kim Suk ki (金锡基)
Korean, South Koreas electronics industry leader, Doctor of Engineering (graduated from the University of Minnesota), Professor of Korea University, previously worked at Bell Labs and Honeywell USA, served as vice president of Samsung Electronics, senior expert in integrated circuit design field, IEEE Senior Member, Vice President of the Korea Institute of Electrical Engineers, Chairman of the Korea Semiconductor Industry Association. Has published more than 250 academic papers with more than 60 patents.
 
Zhu Yanping (朱延平)
Taiwanese, China, Doctor of Engineering (graduated from National Cheng Kung University), Chairman of the Taiwan Cloud Services Association, Director of Information Management Department of National Chung Hsing University. Has won the Youth Invention Award by Taiwan Ministry of Education and Taiwan Top Ten Information Talent Award. Has deeply studied blockchain applications over the years and led a block chain technology team to develop systems for health big data and agricultural traceability projects.
 

Chief Experts

Mo Bing (莫冰)
Chinese, Doctor of Engineering (graduated from Harbin Institute of Technology), Research Professor of Korea University, Distinguished Fellow of Sun Yat - sen University, Internet of Things expert, integrated circuit expert, Senior Member of Chinese Society of Micro-Nano Technology, IEEE Member. Has published more than 20 papers and applied for 18 invention patents. Began his research of BitCoin in 2013, one of the earliest users of btc 38.com and Korea korbit. Served as Technical Director of Korea University to cooperate with Samsung Group to complete the project Multi sensor data interaction and fusion based on peer to peer network. Committed to the integration of block chain technology and Internet of Things to create a real commercialized public chain.
 
Wei Songjie (魏松杰)
Chinese, Doctor of Engineering (graduated from the University of Delaware), Associate Professor of Nanjing University of Science and Technology, Core Member and Master Supervisor of Network Space Security Engineering Research Institute, Block Chain Technology expert in the field of computer network protocol and application, network and information security. Has published more than 20 papers and applied for 7 invention patents. Previously worked at Google, Qualcomm, Bloomberg and many other high-tech companies in the United States, served as R D engineer and technical expert; has a wealth of experience in computer system design, product development and project management.
 

Core Members

Shan Liang (单良)
Graduated from KOREATECH (Korea University of Technology and Education) Mechanical Engineering Department, Venture Capital PhD, GM of Waltonchain Technology Co., Ltd. (Korea), Director of Korea Sungkyun Technology Co., Ltd., Chinese Market Manager of the heating component manufacturer NHTECH, a subsidiary of Samsung SDI, economic group leader of the Friendship Association of Chinese Doctoral Students in Korea, one of the earliest users of Korbit, senior digital money player.
 
Chen Zhangrong (陈樟荣)
Chinese, graduated in Business Management, received a BBA degree in Armstrong University in the United States, President of TIANYU INTERNATIONAL GROUP LIMITED, leader of Chinese clothing accessories industry, Chinas well-known business mentor, guest of the CCTV2 Win in China show in 2008. Researcher in the field of thinking training for Practical Business Intelligence e-commerce and MONEYYOU course, expert on success for Profit Model course. Began to contact Bitcoin in 2013 with a strong interest and in-depth study of digital money and decentralized management thinking. Has a wealth of practical experience in the business management, market research, channel construction, business cooperation and business model.
 
Lin Herui (林和瑞)
Chinese, Dean of Xiamen Zhongchuan Internet of Things Industry Research Institute, Chairman of Xiamen Citylink Technology Co., Ltd., Chairman of Xiamen IOT. He successively served as Nokia RD Manager and Product Manager, Microsoft Hardware Department Supply Chain Director. In 2014, started to set up a number of IoT enterprises and laid out the industrial chain of the Internet of Things. The products and services developed under his guidance are very popular. Assisted the government in carrying out industrial and policy research and participated in planning of multiple government projects of smart cities, IoT towns and project reviews.
 
Ma Xingyi (马兴毅)
Chinese, China Scholarship Council (CSC) special student, Doctor of Engineering of Korea University, Research Professor of Fusion Chemical Systems Institute of Korea University, Korea Sungkyun Technology Co., Ltd. CEO, Member of Korea Industry Association, Associate Member of the Royal Society of Chemistry, has published his research results in the worlds top journal Nature Communications and participated in the preparation of a series of teaching materials for Internet of Things engineering titled Introduction to the Internet of Things. His current research direction covers cross-disciplines that combine blockchain technology with intelligent medical technology.
 
Zhao Haiming (赵海明)
Chinese, Doctor of Chemical Conductive Polymer of Sungkyunkwan University, core member of Korea BK21th conductive polymer project, researcher of Korea Gyeonggi Institute of Sensor, researcher of Korea ECO NCTech Co., Ltd., Vice President of the Chinese Chamber of Commerce, Director of Korea Sungkyun Technology Co., Ltd. He has been engaged in transfer of semiconductor, sensor and other technologies in South Korea. He is an early participant of the digital currency market.
 
Liu Cai (刘才)
Chinese, Master of Engineering, has 12 years of experience in design and verification of VLSI and a wealth of practical project experience in RFID chip design process, SOC chip architecture, digital-analog hybrid circuit design, including algorithm design, RTL design, simulation verification, FPGA prototype verification, DC synthesis, backend PR, package testing, etc. Has led a team to complete the development of a variety of navigation and positioning baseband chips and communication baseband chips, finished a series of AES, DES and other encryption module designs, won the first prize of GNSS and LBS Association of China for scientific and technological progress. Finally, he is an expert in the consensus mechanism principle of blockchain and the related asymmetric encryption algorithm.
 
Yang Feng (杨锋)
Chinese, Master of Engineering, worked at ZTE. Artificial intelligence expert, integrated circuit expert. Has 12 years of experience in VLSI research and development, architecture design and verification and 5 years of research experience in artificial intelligence and the genetic algorithm. Has won the Shenzhen Science and Technology Innovation Award. Has done an in-depth research on the principle and realization of the RFID technology, the underlying infrastructure of blockchain, smart contracts and the consensus mechanism algorithm.
 
Guo Jianping (郭建平)
Chinese, Doctor of Engineering (graduated from the Chinese University of Hong Kong), Associate Professor of the Hundred Talents Program of Sun Yat-sen University, academic advisor of masters degree students, IEEE senior member, integrated circuit expert. Has published more than 40 international journal conference papers in the field of IC design and applied for 16 patents in China.
 
Huang Ruimin (黄锐敏)
Chinese, Doctor of Engineering (graduated from the University of Freiburg, Germany), academic advisor of masters degree students, lecturer of the Department of Electronics of Huaqiao University, integrated circuit expert. Mainly explores digital signal processing circuit and system implementation and works on digital signal processing technology long-term research and development.
 
Guo Rongxin (郭荣新)
Chinese, Master of Engineering, Deputy Director of the Communication Technology Research Center of Huaqiao University. Has more than 10 years of experience in design and development of hardware and software for embedded systems, works on the long-term research and development of RFID and blockchain technology in the field of Internet of Things.
 
Dai Minhua (戴闽华)
Chinese, graduated in Business Management, received a BBA degree from Armstrong University, senior financial expert, served as Vice President and CFO of Tanyu International Group Co., Ltd. Has 13 years of financial work experience, has a wealth of experience in developing and implementing enterprise strategy and business plans, as well as achieving business management objectives and development goals.
 
Liu Dongxin (刘东欣)
Chinese, received an MBA from China Europe International Business School, Visiting Scholar of Kellogg School of Management at Northwestern University, strategic management consulting expert, investment and financing expert. His current research interest lies in the impact of the blockchain technology on the financial sector.
 

Angel Investors

Song Guoping (宋国平)
Qiu Jun (邱俊)
Yan Xiaoqian (严小铅)
Lin Jingwei (林敬伟)
He Honglian (何红连)

Advisory Team

Ko Sang Tae (高尚台)
Liu Xiaowei (刘晓为)
Su Yan (苏岩)
Zhang Yan (张岩)
Ma Pingping (马萍萍)
Peng Xiande (彭先德)
Fu Ke (傅克)
Xiao Guangjian (肖光坚)
Li Xiong (李雄)
 
The Team (pt.I)
The Team - The Engineers (pt. II)
The Team - Angel Investors & Advisors (pt. III)
WaltonChain Office Tour
Meet the team #1: Xu Fangcheng
Meet the team #2: South Korean Team
Meet the team #3: Wei Songjie
Meet the team #4: Suk Ki Kim
Meet the team #5: Lin Herui
Meet the team #6: Bing Mok (CEO)
 

Partnerships, Affiliations & Corporate Interests

Government Affiliations
Fujian IoT Industry Association
Air purification and smart monitoring project with Jinhu Provincial Government
"Smart Oceans" blockchain R&D project with Fujian Provincial Government
Building "Blockchain Silicon Valley" with Taiwan Cloud and Fujian Provincial Government
KISA and Korean IoT research centre
Taiwan Cloud Association
Korea University engineering department
Korea Blockchain Enterprise Promotion Association (authorized by South Korean National Assembly)
 
Smart Logistics / Smart Warehouse
Xiangyu Group
Fuyao Glass Industry Group co., Ltd
Kehua
Lipson Plastic
NanKang City Furniture industry
Direct delivery
Fujian Soonbox Logistics Park
Huodull Technology
 
Smart Retail
Guangdong Original Clothing Trading Center
Shenzhen M&A Association of Listed Companies
Septwolves
Fuguiniao
SMEN
TANYU
JoeOne
Lalabobo
Ishijah
Kaltendin
 
Technical Alliance
Alibaba Cloud
China Mobile IoT Alliance
Xiamen Branch of China Telecom Corporation Limited
Zhangzhou Branch of** China Telecom** Corporation Limited
NC Technologies
Shenzhen Card Cube Smart Technology co., Ltd
NIDS Sensor Technology
Sungkyun Technologies
NH Tech
Jiangsu Zhongke Internet of Things Technology Venture Capital Co., Ltd.
Fujian C-TOP Electronics co., Ltd.
 
Finance
Sinolink Securites
Gingko Capital (Investment Arm of Waltonchain) -> Investments
Gingko Investment List on Reddit
 
Blockchain Partner
Mobius
Freyrchain
Loci
Coinlink
SwftCoin
Morganchain
Aston
 
Media Partner
JU&KE Creative Design
Yunnan Yunshanghuaxia Trading co., Ltd.
ArtCrypto
Fanfangxiang Culture & Media co., Ltd.
 
Waltonchain Government Affiliations Infographic
Waltonchain Business Affiliations Infographic
Summary of Some of Waltonchain's Government and Business Partnerships
 
Child Chains
Freyrchain - Freyrchain - The world’s first blockchain-based collectibles data authenticity platform
Fashionchain Fashionchain - Fashionchain restructures the strongly-centralized pyramid structure inherent in the fashion industry ecology into a decentralized structure in which all parties connect point to point directly.
 
Click here for the News, PR & Awards Thread.
Click here for a Timeline of Official - Waltonchain-Medium - Posts.
 
Videos
Waltonchain Annual Meeting Presentation Video
Waltonchain Introduction Video
Waltonchain Visit and Product Demo! (Part 1 of 2) - Boxmining
Waltonchain Interview and Demo (Part 2 of 2) - Boxmining
Waltonchain Coinnest Meetup with Mo Bing
Dr. Mo Bing's First Live Interview with Coinnest CEO
Waltonchain CEO Mo Bing announcing the official launch of Waltonchain Mainnet
List of AMAs
First Reddit AMA - October 1, 2017
Technical AMA - October 9, 2017
Hardware AMA Summary - October 17,2017
Extended Hardware AMA - October 24, 2017
Retail Demo AMA - November 27, 2017
Masternode AMA - December 7, 2017
Slack AMA Live Thread - January 3, 2018
Waltonchain Beta Release AMA Part 1 - January 5, 2018
Waltonchain Beta Release AMA Part 2 - January 15, 2018
Waltonchain February Q&A - February 18, 2018
Waltonchain March AMA Part 1 - March 19, 2018
Waltonchain March AMA Part 2 - March 27, 2018
Progress Reports
Waltonchain Work Progress in Q2 2018
Waltonchain Work Progress in Q1 2018
Waltonchain: New Logo · New IC strategy ·New Journey!
The Summary of Waltonchain in 2017
Waltonchain Project Progress Report (Nov. – Dec. 2017)
Professor Kim Suk Ki Arrived at Xiamen for Project Review and to Provide Guidance
A letter to the waltonchain family
A Letter from Waltonchain Foundation
Waltonchain Alpha Version Internal Testing
Noteworthy Posts
Waltonchain’s Bigger Picture: OBOR
Waltonchain: Ushering an Era of IoT Mass Market Adoption
What is Waltonchain and Why Should We Care?
Waltonchain and the Chinese Government: Cooperation, Collaboration and a Bright Future
Top 5 Cryptocurrencies Set For Success In 2018 - Invest in Blockchain
 
Exchanges
Binance, Coinnest, HitBTC, LATOKEN, OKEx, Kucoin, COSS, Coinlink, Allcoin, Coinrail, Cobinhood, Huobi
 

Frequently Asked Questions

 
 
Walton Knights
u/fent11
u/NetworkTraveler
u/yayowam
u/Crypto_RALLY
u/TheSideQuest
RikkiTikki (slack)
Crypto Buff (telegram)
submitted by istaan69 to waltonchain [link] [comments]

Why I see Virtcoin as a $200 coin when really considering ASIC resistance

First of all, Vertcoin does indeed have a tremendous community, and this is not to be understated. However, this is only a fraction of the value position of this coin. I just want to expand on the ASIC resistance thing a bit. As an electrical engineer who has actually designed ASIC's, I do have some background on this. What I can tell you is that this term "ASIC Resistant" is that it is a little bit misleading. In theory, any algorithm can be turned into an ASIC. An ASIC or Application Specific Integrated Circuit is a digital or analog or mixed analog digital circuit that has been cast into Sea of Gates, Semi-Custom, or Full Custom ASIC technology. The cheapest route is Sea of Gates. If one didn't want to do a Sea of Gates ASIC, they could implement an algorithm in a FPGA, or Field Programmable Gate Array. Altera and Xilinx are the dominant players here. In the early days of Bitcoin, there were many FPGA miners, this was a very common way to mine Bitcoin.
Overall, It takes somewhere between USD $50,000 to $1,000,000 to make an ASIC. It's an expensive process. There is a tremendous amount of engineering, where the circuit is designed in System Verilog, Verilog or VHDL, and very extensive testbenches to make sure that the when the chip is made it works the first time. Engineers prototype ASICs in FPGA's, and the development boards for ASIC emulation can cost $20k or more just in themselves. Then the design goes to a foundry where the chip is made, and that will be expensive, $50k to $500k. So there has to be motivation to make an ASIC, such as high volume chip sales. For Sea of Gates technology, a rule of thumb is that there is typically a break even point when a company sells 1,000 to 2,000 chips a year that has been made into an ASIC. That is because Sea of Gates is about a $100k process.
The ASIC Resistance of Vertcoin is not technology related, i.e. the algorithm that is currently being used could be made into an ASIC. What makes Vertcoin ASIC resistance is the commitment of the team to change the algorithm if someone does make an ASIC to mine Vertcoin. This is what gives Vertcoin it's value position. I really appreciate that! This is a de-facto way to limit the power of miners, in one simple swipe.
How wants to deal with this Bitcoin forking situation anymore? At this point, with the upcoming fork, it seems more and more unnecessary. I see Bitcoin as a storage of value layer, and other coins such as VTC and LTC as transaction layer coins.
To me what gives VTC value is the intention of the community AND the consequent action of it.
submitted by TeslaCrytpo to vertcoin [link] [comments]

AMD's Growing CPU Advantage Over Intel

https://seekingalpha.com/article/4152240-amds-growing-cpu-advantage-intel?page=1
AMD's Growing CPU Advantage Over Intel Mar. 1.18 | About: Advanced Micro (AMD)
Raymond Caron, Ph.D. Tech, solar, natural resources, energy (315 followers) Summary AMD's past and economic hazards. AMD's Current market conditions. AMD Zen CPU advantage over Intel. AMD is primarily a CPU fabrication company with much experience and a great history in that respect. They hold patents for 64-bit processing, as well as ARM based processing patents, and GPU architecture patents. AMD built a name for itself in the mid-to-late 90’s when they introduced the K-series CPU’s to good reviews followed by the Athlon series in ‘99. AMD was profitable, they bought the companies NexGen, Alchemy Semiconductor, and ATI. Past Economic Hazards If AMD has such a great history, then what happened? Before I go over the technical advantage that AMD has over Intel, it’s worth looking to see how AMD failed in the past, and to see if those hazards still present a risk to AMD. As for investment purposes we’re more interested in AMD’s turning a profit. AMD suffered from intermittent CPU fabrication problems, and was also the victim of sustained anti-competitive behaviour from Intel who interfered with AMD’s attempts to sell its CPU’s to the market through Sony, Hitachi, Toshiba, Fujitsu, NEC, Dell, Gateway, HP, Acer, and Lenovo. Intel was investigated and/or fined by multiple countries including Japan, Korea, USA, and EU. These hazard needs to be examined to see if history will repeat itself. There have been some rather large changes in the market since then.
1) The EU has shown they are not averse to leveling large fines, and Intel is still fighting the guilty verdict from the last EU fine levied against them; they’ve already lost one appeal. It’s conceivable to expect that the EU, and other countries, would prosecute Intel again. This is compounded by the recent security problems with Intel CPU’s and the fact that Intel sold these CPU’s under false advertising as secure when Intel knew they were not. Here are some of the largest fines dished out by the EU
2) The Internet has evolved from Web 1.0 to 2.0. Consumers are increasing their online presence each year. This reduces the clout that Intel can wield over the market as AMD can more easily sell to consumers through smaller Internet based companies.
3) Traditional distributors (HP, Dell, Lenovo, etc.) are struggling. All of these companies have had recent issues with declining revenue due to Internet competition, and ARM competition. These companies are struggling for sales and this reduces the clout that Intel has over them, as Intel is no longer able to ensure their future. It no longer pays to be in the club. These points are summarized in the graph below, from Statista, which shows “ODM Direct” sales and “other sales” increasing their market share from 2009 to Q3 2017. 4) AMD spun off Global Foundries as a separate company. AMD has a fabrication agreement with Global Foundries, but is also free to fabricate at another foundry such as TSMC, where AMD has recently announced they will be printing Vega at 7nm.
5) Global Foundries developed the capability to fabricate at 16nm, 14nm, and 12nm alongside Samsung, and IBM, and bought the process from IBM to fabricate at 7nm. These three companies have been cooperating to develop new fabrication nodes.
6) The computer market has grown much larger since the mid-90’s – 2006 when AMD last had a significant tangible advantage over Intel, as computer sales rose steadily until 2011 before starting a slow decline, see Statista graph below. The decline corresponds directly to the loss of competition in the marketplace between AMD and Intel, when AMD released the Bulldozer CPU in 2011. Tablets also became available starting in 2010 and contributed to the fall in computer sales which started falling in 2012. It’s important to note that computer shipments did not fall in 2017, they remained static, and AMD’s GPU market share rose in Q4 2017 at the expense of Nvidia and Intel.
7) In terms of fabrication, AMD has access to 7nm on Global Foundries as well as through TSMC. It’s unlikely that AMD will experience CPU fabrication problems in the future. This is something of a reversal of fortunes as Intel is now experiencing issues with its 10nm fabrication facilities which are behind schedule by more than 2 years, and maybe longer. It would be costly for Intel to use another foundry to print their CPU’s due to the overhead that their current foundries have on their bottom line. If Intel is unable to get the 10nm process working, they’re going to have difficulty competing with AMD. AMD: Current market conditions In 2011 AMD released its Bulldozer line of CPU’s to poor reviews and was relegated to selling on the discount market where sales margins are low. Since that time AMD’s profits have been largely determined by the performance of its GPU and Semi-Custom business. Analysts have become accustomed to looking at AMD’s revenue from a GPU perspective, which isn’t currently being seen in a positive light due to the relation between AMD GPU’s and cryptocurrency mining.
The market views cryptocurrency as further risk to AMD. When Bitcoin was introduced it was also mined with GPU’s. When the currency switched to ASIC circuits (a basic inexpensive and simple circuit) for increased profitability (ASIC’s are cheaper because they’re simple), the GPU’s purchased for mining were resold on the market and ended up competing with and hurting new AMD GPU sales. There is also perceived risk to AMD from Nvidia which has favorable reviews for its Pascal GPU offerings. While AMD has been selling GPU’s they haven’t increased GPU supply due to cryptocurrency demand, while Nvidia has. This resulted in a very high cost for AMD GPU’s relative to Nvidia’s. There are strategic reasons for AMD’s current position:
1) While the AMD GPU’s are profitable and greatly desired for cryptocurrency mining, AMD’s market access is through 3rd party resellers whom enjoy the revenue from marked-up GPU sales. AMD most likely makes lower margins on GPU sales relative to the Zen CPU sales due to higher fabrication costs associated with the fabrication of larger size dies and the corresponding lower yield. For reference I’ve included the size of AMD’s and Nvidia’s GPU’s as well as AMD’s Ryzen CPU and Intel’s Coffee lake 8th generation CPU. This suggests that if AMD had to pick and choose between products, they’d focus on Zen due higher yield and revenue from sales and an increase in margin.
2) If AMD maintained historical levels of GPU production in the face of cryptocurrency demand, while increasing production for Zen products, they would maximize potential income for highest margin products (EPYC), while reducing future vulnerability to second-hand GPU sales being resold on the market. 3) AMD was burned in the past from second hand GPU’s and want to avoid repeating that experience. AMD stated several times that the cryptocurrency boom was not factored into forward looking statements, meaning they haven’t produced more GPU’s to expect more GPU sales.
In contrast, Nvidia increased its production of GPU’s due to cryptocurrency demand, as AMD did in the past. Since their Pascal GPU has entered its 2nd year on the market and is capable of running video games for years to come (1080p and 4k gaming), Nvidia will be entering a position where they will be competing directly with older GPU’s used for mining, that are as capable as the cards Nvidia is currently selling. Second-hand GPU’s from mining are known to function very well, with only a need to replace the fan. This is because semiconductors work best in a steady state, as opposed to being turned on and off, so it will endure less wear when used 24/7.
The market is also pessimistic regarding AMD’s P/E ratio. The market is accustomed to evaluating stocks using the P/E ratio. This statistical test is not actually accurate in evaluating new companies, or companies going into or coming out of bankruptcy. It is more accurate in evaluating companies that have a consistent business operating trend over time.
“Similarly, a company with very low earnings now may command a very high P/E ratio even though it isn’t necessarily overvalued. The company may have just IPO’d and growth expectations are very high, or expectations remain high since the company dominates the technology in its space.” P/E Ratio: Problems With The P/E I regard the pessimism surrounding AMD stock due to GPU’s and past history as a positive trait, because the threat is minor. While AMD is experiencing competitive problems with its GPU’s in gaming AMD holds an advantage in Blockchain processing which stands to be a larger and more lucrative market. I also believe that AMD’s progress with Zen, particularly with EPYC and the recent Meltdown related security and performance issues with all Intel CPU offerings far outweigh any GPU turbulence. This turns the pessimism surrounding AMD regarding its GPU’s into a stock benefit. 1) A pessimistic group prevents the stock from becoming a bubble. -It provides a counter argument against hype relating to product launches that are not proven by earnings. Which is unfortunately a historical trend for AMD as they have had difficulty selling server CPU’s, and consumer CPU’s in the past due to market interference by Intel. 2) It creates predictable daily, weekly, monthly, quarterly fluctuations in the stock price that can be used, to generate income. 3) Due to recent product launches and market conditions (Zen architecture advantage, 12nm node launching, Meltdown performance flaw affecting all Intel CPU’s, Intel’s problems with 10nm) and the fact that AMD is once again selling a competitive product, AMD is making more money each quarter. Therefore the base price of AMD’s stock will rise with earnings, as we’re seeing. This is also a form of investment security, where perceived losses are returned over time, due to a stock that is in a long-term upward trajectory due to new products reaching a responsive market.
4) AMD remains a cheap stock. While it’s volatile it’s stuck in a long-term upward trend due to market conditions and new product launches. An investor can buy more stock (with a limited budget) to maximize earnings. This is advantage also means that the stock is more easily manipulated, as seen during the Q3 2017 ER.
5) The pessimism is unfounded. The cryptocurrency craze hasn’t died, it increased – fell – and recovered. The second hand market did not see an influx of mining GPU’s as mining remains profitable.
6) Blockchain is an emerging market, that will eclipse the gaming market in size due to the wide breath of applications across various industries. Vega is a highly desired product for Blockchain applications as AMD has retained a processing and performance advantage over Nvidia. There are more and rapidly growing applications for Blockchain every day, all (or most) of which will require GPU’s. For instance Microsoft, The Golem supercomputer, IBM, HP, Oracle, Red Hat, and others. Long-term upwards trend AMD is at the beginning of a long-term upward trend supported by a comprehensive and competitive product portfolio that is still being delivered to the market, AMD referred to this as product ramping. AMD’s most effective products with Zen is EPYC, and the Raven Ridge APU. EPYC entered the market in mid-December and was completely sold out by mid-January, but has since been restocked. Intel remains uncompetitive in that industry as their CPU offerings are retarded by a 40% performance flaw due to Meltdown patches. Server CPU sales command the highest margins for both Intel and AMD.
The AMD Raven Ridge APU was recently released to excellent reviews. The APU is significant due to high GPU prices driven buy cryptocurrency, and the fact that the APU is a CPU/GPU hybrid which has the performance to play games available today at 1080p. The APU also supports the Vulcan API, which can call upon multiple GPU’s to increase performance, so a system can be upgraded with an AMD or Nvidia GPU that supports Vulcan API at a later date for increased performance for those games or workloads that been programmed to support it. Or the APU can be replaced when the prices of GPU’s fall.
AMD also stands to benefit as Intel confirmed that their new 10 nm fabrication node is behind in technical capability relative to the Samsung, TSMC, and Global Foundries 7 nm fabrication process. This brings into questions Intel’s competitiveness in 2019 and beyond. Take-Away • AMD was uncompetitive with respect to CPU’s from 2011 to 2017 • When AMD was competitive, from 1996 to 2011 they did record profit and bought 3 companies including ATI. • AMD CPU business suffered from: • Market manipulation from Intel. • Intel fined by EU, Japan, Korea, and settled with the USA • Foundry productivity and upgrade complications • AMD has changed • Global Foundries spun off as an independent business • Has developed 14nm &12nm, and is implementing 7nm fabrication • Intel late on 10nm, is less competitive than 7nm node • AMD to fabricate products using multiple foundries (TSMC, Global Foundries) • The market has changed • More AMD products are available on the Internet and both the adoption of the Internet and the size of the Internet retail market has exploded, thanks to the success of smartphones and tablets. • Consumer habits have changed, more people shop online each year. Traditional retailers have lost market share. • Computer market is larger (on-average), but has been declining. While Computer shipments declined in Q2 and Q3 2017, AMD sold more CPU’s. • AMD was uncompetitive with respect to CPU’s from 2011 to 2017. • Analysts look to GPU and Semi-Custom sales for revenue. • Cryptocurrency boom intensified, no crash occurred. • AMD did not increase GPU production to meet cryptocurrency demand. • Blockchain represents a new growth potential for AMD GPU’s. • Pessimism acts as security against a stock bubble & corresponding bust. • Creates cyclical volatility in the stock that can be used to generate profit. • P/E ratio is misleading when used to evaluate AMD. • AMD has long-term growth potential. • 2017 AMD releases competitive product portfolio. • Since Zen was released in March 2017 AMD has beat ER expectations. • AMD returns to profitability in 2017. • AMD taking measureable market share from Intel in OEM CPU Desktop and in CPU market. • High margin server product EPYC released in December 2017 before worst ever CPU security bug found in Intel CPU’s that are hit with detrimental 40% performance patch. • Ryzen APU (Raven Ridge) announced in February 2018, to meet gaming GPU shortage created by high GPU demand for cryptocurrency mining. • Blockchain is a long-term growth opportunity for AMD. • Intel is behind the competition for the next CPU fabrication node. AMD’s growing CPU advantage over Intel About AMD’s Zen Zen is a technical breakthrough in CPU architecture because it’s a modular design and because it is a small CPU while providing similar or better performance than the Intel competition.
Since Zen was released in March 2017, we’ve seen AMD go from 18% CPU market share in the OEM consumer desktops to essentially 50% market share, this was also supported by comments from Lisa Su during the Q3 2017 ER call, by MindFactory.de, and by Amazon sales of CPU’s. We also saw AMD increase its market share of total desktop CPU’s. We also started seeing market share flux between AMD and Intel as new CPU’s are released. Zen is a technical breakthrough supported by a few general guidelines relating to electronics. This provides AMD with an across the board CPU market advantage over Intel for every CPU market addressed.
1) The larger the CPU the lower the yield. - Zen architecture that makes up Ryzen, Threadripper, and EPYC is smaller (44 mm2 compared to 151 mm2 for Coffee Lake). A larger CPU means fewer CPU’s made during fabrication per wafer. AMD will have roughly 3x the fabrication yield for each Zen printed compared to each Coffee Lake printed, therefore each CPU has a much lower cost of manufacturing.
2) The larger the CPU the harder it is to fabricate without errors. - The chance that a CPU will be perfectly fabricated falls exponentially with increasing surface area. Intel will have fewer high quality CPU’s printed compared to AMD. This means that AMD will make a higher margin on each CPU sold. AMD’s supply of perfect printed Ryzen’s (1800X) are so high that the company had to give them away at a reduced cost in order to meet supply demands for the cheaper Ryzen 5 1600X. If you bought a 1600X in August/September, you probably ended up with an 1800X.
3) Larger CPU’s are harder to fabricate without errors on smaller nodes. -The technical capability to fabricate CPU’s at smaller nodes becomes more difficult due to the higher precision that is required to fabricate at a smaller node, and due to the corresponding increase in errors. “A second reason for the slowdown is that it’s simply getting harder to design, inspect and test chips at advanced nodes. Physical effects such as heat, electrostatic discharge and electromagnetic interference are more pronounced at 7nm than at 28nm. It also takes more power to drive signals through skinny wires, and circuits are more sensitive to test and inspection, as well as to thermal migration across a chip. All of that needs to be accounted for and simulated using multi-physics simulation, emulation and prototyping.“ Is 7nm The Last Major Node? “Simply put, the first generation of 10nm requires small processors to ensure high yields. Intel seems to be putting the smaller die sizes (i.e. anything under 15W for a laptop) into the 10nm Cannon Lake bucket, while the larger 35W+ chips will be on 14++ Coffee Lake, a tried and tested sub-node for larger CPUs. While the desktop sits on 14++ for a bit longer, it gives time for Intel to further develop their 10nm fabrication abilities, leading to their 10+ process for larger chips by working their other large chip segments (FPGA, MIC) first.” There are plenty of steps where errors can be created within a fabricated CPU. This is most likely the culprit behind Intel’s inability to launch its 10nm fabrication process. They’re simply unable to print such a large CPU on such a small node with high enough yields to make the process competitive. Intel thought they were ahead of the competition with respect to printing large CPU’s on a small node, until AMD avoided the issue completely by designing a smaller modular CPU. Intel avoided any mention of its 10nm node during its Q4 2017 ER, which I interpret as bad news for Intel shareholders. If you have nothing good to say, then you don’t say anything. Intel having nothing to say about something that is fundamentally critical to its success as a company can’t be good. Intel is on track however to deliver hybrid CPU’s where some small components are printed on 10nm. It’s recently also come to light that Intel’s 10nm node is less competitive than the Global Foundries, Samsung, and TSMC 7nm nodes, which means that Intel is now firmly behind in CPU fabrication. 4) AMD Zen is a new architecture built from the ground up. Intel’s CPU’s are built on-top of older architecture developed with 30-yr old strategies, some of which we’ve recently discovered are flawed. This resulted in the Meltdown flaw, the Spectre flaws, and also includes the ME, and AMT bugs in Intel CPU’s. While AMD is still affected by Spectre, AMD has only ever acknowledged that they’re completely susceptible to Spectre 1, as AMD considers Spectre 2 to be difficult to exploit on an AMD Zen CPU. “It is much more difficult on all AMD CPUs, because BTB entries are not aliased - the attacker must know (and be able to execute arbitrary code at) the exact address of the targeted branch instruction.” Technical Analysis of Spectre & Meltdown * Amd Further reading Spectre and Meltdown: Linux creator Linus Torvalds criticises Intel's 'garbage' patches | ZDNet FYI: Processor bugs are everywhere - just ask Intel and AMD Meltdown and Spectre: Good news for AMD users, (more) bad news for Intel Cybersecurity agency: The only sure defense against huge chip flaw is a new chip Kernel-memory-leaking Intel processor design flaw forces Linux, Windows redesign Take-Away • AMD Zen enjoys a CPU fabrication yield advantage over Intel • AMD Zen enjoys higher yield of high quality CPU’s • Intel’s CPU’s are affected with 40% performance drop due to Meltdown flaw that affect server CPU sales.
AMD stock drivers 1) EPYC • -A critically acclaimed CPU that is sold at a discount compared to Intel. • -Is not affected by 40% software slow-downs due to Meltdown. 2) Raven Ridge desktop APU • - Targets unfed GPU market which has been stifled due to cryptocurrency demand - Customers can upgrade to a new CPU or add a GPU at a later date without changing the motherboard. • - AM4 motherboard supported until 2020. 3) Vega GPU sales to Intel for 8th generation CPU’s with integrated graphics. • - AMD gains access to the complete desktop and mobile market through Intel.
4) Mobile Ryzen APU sales • -Providing gaming capability in a compact power envelope.
5) Ryzen and Threadripper sales • -Fabricated on 12nm in April. • -May eliminate Intel’s last remaining CPU advantage in IPC single core processing. • -AM4 motherboard supported until 2020. • -7nm Ryzen on track for early 2019. 6) Others: Vega, Polaris, Semi-custom, etc. • -I consider any positive developments here to be gravy. Conclusion While in the past Intel interfered with AMD's ability to bring it's products to market, the market has changed. The internet has grown significantly and is now a large market that dominates when in computer sales. It's questionable if Intel still has the influence to affect this new market, and doing so would most certainly result in fines and further bad press.
AMD's foundry problems were turned into an advantage over Intel.
AMD's more recent past was heavily influenced by the failure of the Bulldozer line of CPU's that dragged on AMD's bottom line from 2011 to 2017.
AMD's Zen line of CPU's is a breakthrough that exploits an alternative, superior strategy, in chip design which results in a smaller CPU. A smaller CPU enjoys compounded yield and quality advantages over Intel's CPU architecture. Intel's lead in CPU performance will at the very least be challenged and will more likely come to an end in 2018, until they release a redesigned CPU.
I previously targeted AMD to be worth $20 by the end of Q4 2017 ER. This was based on the speed that Intel was able to get products to market, in comparison AMD is much slower. I believe the stock should be there, but the GPU related story was prominent due to cryptocurrency craze. Financial analysts need more time to catch on to what’s happening with AMD, they need an ER that is driven by CPU sales. I believe that the Q1 2018 is the ER to do that. AMD had EPYC stock in stores when the Meltdown and Spectre flaws hit the news. These CPU’s were sold out by mid-January and are large margin sales.
There are many variables at play within the market, however barring any disruptions I’d expect that AMD will be worth $20 at some point in 2018 due these market drivers. If AMD sold enough EPYC CPU’s due to Intel’s ongoing CPU security problems, then it may occur following the ER in Q1 2018. However, if anything is customary with AMD, it’s that these things always take longer than expected.
submitted by kchia124 to AMD_Stock [link] [comments]

The good chance of Free Trial about VEO by Blackminer F1 is coming&revenue $5.3

The revenue of VEO is rising to $5.3/day, it's a good chance of Free Trial by Blackminer F1 This is the entrance to the trial mining: https://www.hashaltcoin.com/en/trial_miners/2
Today's profit of VEO is very satisfying, i would like to share some opinion about the VEO, and you can judge whether Trial it for free or not.
VEO is a fully mining public chain without pre-mining. Zack, the main developer of the project,who also uesed to be the formar first CTO of AE , did not mine any tokens in advance during programming. We believe that the VEO would be much valuable in the future.
So now ,you have a great chance to mine it by Blackminer F1 for free, even get one in your pocket as a lotto ticket.
You can download the wallet here: https://myveowallet.com/
The following is some details about Blackminer F1
In September 2018, Blackminer's first batch of FPGA miners was officially launched, model Blackminer F1. Currently there are 22 algorithms built in. The price is $2000, all in stock. The newly released version of Blackminer F1 is F1+, which comes with three boards and can support same algorithms as Blackminer F1. But with newly updated hardware design, its performance is about 1.6 to 1.8 times of one F1.
You can check the daily profit by this page: https://www.hashaltcoin.com/en/calculation
There are some third party reviews:
ruplikmastik666's test review: https://bitcointalk.org/index.php?topic=5039924.0 Bittawm's review: https://bitcointalk.org/index.php?topic=5065403.msg47689832#msg47689832 The Bitcoin Miner Youtube channel review: https://youtu.be/lK2aACwneks
The official Links:
Official Website: https://hashaltcoin.com/ Official Discord: https://discord.gg/eUNRSgy (very active, mainly to share and discover innovative cryptos and announce development progress) Bitcointalk ANN: https://bitcointalk.org/index.php?topic=5029989.0
Sales Manager : Lili whatsapp:+8618612535678
submitted by miningfans to Amoveo [link] [comments]

Antminer S9 no longer hashing?

Good morning folks,
I have an Antminer S9 that has performed flawlessly. After I moved it to a better location, I noticed that it no longer seems to be working. The green light is flashing, but it doesn't seem to be hashing to my pool (Nicehash).
I'm fairly new to Bitcoining mining and can't make sense of some of the information on my status screen. Before I jump into Bitmain support, I was wondering if anyone could clue me in as to what the problem might be.
https://s15.postimg.cc/i0n5qsyoInked_Capture_LI.jpg
I'll post my Kernal Log here.
Thank you in advance!!!
KERNAL LOG: [ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 3.14.0-xilinx-ge8a2f71-dirty ([email protected]) (gcc version 4.8.3 20140320 (prerelease) (Sourcery CodeBench Lite 2014.05-23) ) #82 SMP PREEMPT Tue May 16 19:49:53 CST 2017
[ 0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Machine model: Xilinx Zynq
[ 0.000000] cma: CMA: reserved 128 MiB at 27800000
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] On node 0 totalpages: 258048
[ 0.000000] free_area_init_node: node 0, pgdat c0740a40, node_mem_map e6fd8000
[ 0.000000] Normal zone: 1520 pages used for memmap
[ 0.000000] Normal zone: 0 pages reserved
[ 0.000000] Normal zone: 194560 pages, LIFO batch:31
[ 0.000000] HighMem zone: 496 pages used for memmap
[ 0.000000] HighMem zone: 63488 pages, LIFO batch:15
[ 0.000000] PERCPU: Embedded 8 pages/cpu @e6fc0000 s9088 r8192 d15488 u32768
[ 0.000000] pcpu-alloc: s9088 r8192 d15488 u32768 alloc=8*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 256528
[ 0.000000] Kernel command line: noinitrd mem=1008M console=ttyPS0,115200 root=ubi0:rootfs ubi.mtd=1 rootfstype=ubifs rw rootwait
[ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Memory: 884148K/1032192K available (5032K kernel code, 283K rwdata, 1916K rodata, 204K init, 258K bss, 148044K reserved, 253952K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xf0000000 - 0xff000000 ( 240 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xef800000 ( 760 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc06d1374 (6949 kB)
[ 0.000000] .init : 0xc06d2000 - 0xc0705380 ( 205 kB)
[ 0.000000] .data : 0xc0706000 - 0xc074cf78 ( 284 kB)
[ 0.000000] .bss : 0xc074cf84 - 0xc078d9fc ( 259 kB)
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] Dump stacks of tasks blocking RCU-preempt GP.
[ 0.000000] RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] ps7-slcr mapped to f0004000
[ 0.000000] zynq_clock_init: clkc starts at f0004100
[ 0.000000] Zynq clock init
[ 0.000015] sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 3298534883328ns
[ 0.000308] ps7-ttc #0 at f0006000, irq=43
[ 0.000618] Console: colour dummy device 80x30
[ 0.000658] Calibrating delay loop... 1325.46 BogoMIPS (lpj=6627328)
[ 0.040207] pid_max: default: 32768 minimum: 301
[ 0.040436] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.040459] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.042612] CPU: Testing write buffer coherency: ok
[ 0.042974] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.043036] Setting up static identity map for 0x4c4b00 - 0x4c4b58
[ 0.043263] L310 cache controller enabled
[ 0.043282] l2x0: 8 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x72760000, Cache size: 512 kB
[ 0.121037] CPU1: Booted secondary processor
[ 0.210227] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.210357] Brought up 2 CPUs
[ 0.210376] SMP: Total of 2 processors activated.
[ 0.210385] CPU: All CPU(s) started in SVC mode.
[ 0.211051] devtmpfs: initialized
[ 0.213481] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
[ 0.214724] regulator-dummy: no parameters
[ 0.223736] NET: Registered protocol family 16
[ 0.226067] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.228361] cpuidle: using governor ladder
[ 0.228374] cpuidle: using governor menu
[ 0.235908] syscon f8000000.ps7-slcr: regmap [mem 0xf8000000-0xf8000fff] registered
[ 0.237440] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
[ 0.237453] hw-breakpoint: maximum watchpoint size is 4 bytes.
[ 0.237572] zynq-ocm f800c000.ps7-ocmc: ZYNQ OCM pool: 256 KiB @ 0xf0080000
[ 0.259435] bio: create slab at 0
[ 0.261172] vgaarb: loaded
[ 0.261915] SCSI subsystem initialized
[ 0.262814] usbcore: registered new interface driver usbfs
[ 0.262985] usbcore: registered new interface driver hub
[ 0.263217] usbcore: registered new device driver usb
[ 0.263743] media: Linux media interface: v0.10
[ 0.263902] Linux video capture interface: v2.00
[ 0.264150] pps_core: LinuxPPS API ver. 1 registered
[ 0.264162] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <[[email protected]](mailto:[email protected])>
[ 0.264286] PTP clock support registered
[ 0.264656] EDAC MC: Ver: 3.0.0
[ 0.265719] Advanced Linux Sound Architecture Driver Initialized.
[ 0.268708] DMA-API: preallocated 4096 debug entries
[ 0.268724] DMA-API: debugging enabled by kernel config
[ 0.268820] Switched to clocksource arm_global_timer
[ 0.289596] NET: Registered protocol family 2
[ 0.290280] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.290375] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[ 0.290535] TCP: Hash tables configured (established 8192 bind 8192)
[ 0.290612] TCP: reno registered
[ 0.290633] UDP hash table entries: 512 (order: 2, 16384 bytes)
[ 0.290689] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[ 0.290971] NET: Registered protocol family 1
[ 0.291346] RPC: Registered named UNIX socket transport module.
[ 0.291359] RPC: Registered udp transport module.
[ 0.291368] RPC: Registered tcp transport module.
[ 0.291376] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.291391] PCI: CLS 0 bytes, default 64
[ 0.291857] hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
[ 0.293945] futex hash table entries: 512 (order: 3, 32768 bytes)
[ 0.295408] bounce pool size: 64 pages
[ 0.296323] jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
[ 0.296525] msgmni has been set to 1486
[ 0.297330] io scheduler noop registered
[ 0.297343] io scheduler deadline registered
[ 0.297385] io scheduler cfq registered (default)
[ 0.308358] dma-pl330 f8003000.ps7-dma: Loaded driver for PL330 DMAC-2364208
[ 0.308380] dma-pl330 f8003000.ps7-dma: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
[ 0.434378] e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 82, base_baud = 3124999) is a xuartps
[ 1.006815] console [ttyPS0] enabled
[ 1.011106] xdevcfg f8007000.ps7-dev-cfg: ioremap 0xf8007000 to f0068000
[ 1.018731] [drm] Initialized drm 1.1.0 20060810
[ 1.036029] brd: module loaded
[ 1.045494] loop: module loaded
[ 1.055163] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 1.060985] e1000e: Copyright(c) 1999 - 2013 Intel Corporation.
[ 1.068779] libphy: XEMACPS mii bus: probed
[ 1.073341] ------------- phy_id = 0x3625e62
[ 1.078112] xemacps e000b000.ps7-ethernet: pdev->id -1, baseaddr 0xe000b000, irq 54
[ 1.087072] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 1.093912] ehci-pci: EHCI PCI platform driver
[ 1.101155] zynq-dr e0002000.ps7-usb: Unable to init USB phy, missing?
[ 1.107952] usbcore: registered new interface driver usb-storage
[ 1.114850] mousedev: PS/2 mouse device common for all mice
[ 1.120975] i2c /dev entries driver
[ 1.127946] zynq-edac f8006000.ps7-ddrc: ecc not enabled
[ 1.133474] cpufreq_cpu0: failed to get cpu0 regulator: -19
[ 1.139426] Xilinx Zynq CpuIdle Driver started
[ 1.144261] sdhci: Secure Digital Host Controller Interface driver
[ 1.150384] sdhci: Copyright(c) Pierre Ossman
[ 1.154700] sdhci-pltfm: SDHCI platform and OF driver helper
[ 1.161601] mmc0: no vqmmc regulator found
[ 1.165614] mmc0: no vmmc regulator found
[ 1.208845] mmc0: SDHCI controller on e0100000.ps7-sdio [e0100000.ps7-sdio] using ADMA
[ 1.217539] usbcore: registered new interface driver usbhid
[ 1.223054] usbhid: USB HID core driver
[ 1.227806] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda
[ 1.234107] nand: Micron MT29F2G08ABAEAWP
[ 1.238074] nand: 256MiB, SLC, page size: 2048, OOB size: 64
[ 1.244027] Bad block table found at page 131008, version 0x01
[ 1.250251] Bad block table found at page 130944, version 0x01
[ 1.256303] 3 ofpart partitions found on MTD device pl353-nand
[ 1.262080] Creating 3 MTD partitions on "pl353-nand":
[ 1.267174] 0x000000000000-0x000002000000 : "BOOT.bin-env-dts-kernel"
[ 1.275230] 0x000002000000-0x00000b000000 : "angstram-rootfs"
[ 1.282582] 0x00000b000000-0x000010000000 : "upgrade-rootfs"
[ 1.291630] TCP: cubic registered
[ 1.294869] NET: Registered protocol family 17
[ 1.299597] Registering SWP/SWPB emulation handler
[ 1.305497] regulator-dummy: disabling
[ 1.309875] UBI: attaching mtd1 to ubi0
[ 1.836565] UBI: scanning is finished
[ 1.848221] UBI: attached mtd1 (name "angstram-rootfs", size 144 MiB) to ubi0
[ 1.855302] UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
[ 1.862063] UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
[ 1.868728] UBI: VID header offset: 2048 (aligned 2048), data offset: 4096
[ 1.875605] UBI: good PEBs: 1152, bad PEBs: 0, corrupted PEBs: 0
[ 1.881586] UBI: user volume: 1, internal volumes: 1, max. volumes count: 128
[ 1.888693] UBI: max/mean erase counter: 4/1, WL threshold: 4096, image sequence number: 1134783803
[ 1.897736] UBI: available PEBs: 0, total reserved PEBs: 1152, PEBs reserved for bad PEB handling: 40
[ 1.906953] UBI: background thread "ubi_bgt0d" started, PID 1080
[ 1.906959] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[ 1.911038] ALSA device list:
[ 1.911042] No soundcards found.
[ 1.927420] UBIFS: background thread "ubifs_bgt0_0" started, PID 1082
[ 1.956473] UBIFS: recovery needed
[ 2.016970] UBIFS: recovery completed
[ 2.020709] UBIFS: mounted UBI device 0, volume 0, name "rootfs"
[ 2.026635] UBIFS: LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes
[ 2.035771] UBIFS: FS size: 128626688 bytes (122 MiB, 1013 LEBs), journal size 9023488 bytes (8 MiB, 72 LEBs)
[ 2.045653] UBIFS: reserved for root: 0 bytes (0 KiB)
[ 2.050693] UBIFS: media format: w4/r0 (latest is w4/r0), UUID B079DD56-06BB-4E31-8F5E-A6604F480DB2, small LPT model
[ 2.061987] VFS: Mounted root (ubifs filesystem) on device 0:11.
[ 2.069184] devtmpfs: mounted
[ 2.072297] Freeing unused kernel memory: 204K (c06d2000 - c0705000)
[ 2.920928] random: dd urandom read with 0 bits of entropy available
[ 3.318860]
[ 3.318860] bcm54xx_config_init
[ 3.928853]
[ 3.928853] bcm54xx_config_init
[ 7.929682] xemacps e000b000.ps7-ethernet: Set clk to 124999998 Hz
[ 7.935787] xemacps e000b000.ps7-ethernet: link up (1000/FULL)
[ 22.563181] In axi fpga driver!
[ 22.566260] request_mem_region OK!
[ 22.569676] AXI fpga dev virtual address is 0xf01fe000
[ 22.574751] *base_vir_addr = 0x8c510
[ 22.590723] In fpga mem driver!
[ 22.593791] request_mem_region OK!
[ 22.597361] fpga mem virtual address is 0xf3000000
[ 23.408156]
[ 23.408156] bcm54xx_config_init
[ 24.038071]
[ 24.038071] bcm54xx_config_init
[ 28.038487] xemacps e000b000.ps7-ethernet: Set clk to 124999998 Hz
[ 28.044593] xemacps e000b000.ps7-ethernet: link up (1000/FULL)
This is XILINX board. Totalram: 1039794176
Detect 1GB control board of XILINX
DETECT HW version=0008c510
miner ID : 8118b4c610358854
Miner Type = S9
AsicType = 1387
real AsicNum = 63
use critical mode to search freq...
get PLUG ON=0x000000e0
Find hashboard on Chain[5]
Find hashboard on Chain[6]
Find hashboard on Chain[7]
set_reset_allhashboard = 0x0000ffff
Check chain[5] PIC fw version=0x03
Check chain[6] PIC fw version=0x03
Check chain[7] PIC fw version=0x03
chain[5]: [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255]
has freq in PIC, will disable freq setting.
chain[5] has freq in PIC and will jump over...
Chain[5] has core num in PIC
Chain[5] ASIC[15] has core num=5
Check chain[5] PIC fw version=0x03
chain[6]: [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255]
has freq in PIC, will disable freq setting.
chain[6] has freq in PIC and will jump over...
Chain[6] has core num in PIC
Chain[6] ASIC[17] has core num=8
Check chain[6] PIC fw version=0x03
chain[7]: [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255]
has freq in PIC, will disable freq setting.
chain[7] has freq in PIC and will jump over...
Chain[7] has core num in PIC
Chain[7] ASIC[8] has core num=13
Chain[7] ASIC[9] has core num=11
Chain[7] ASIC[13] has core num=11
Chain[7] ASIC[19] has core num=14
Chain[7] ASIC[30] has core num=6
Chain[7] ASIC[32] has core num=1
Chain[7] ASIC[42] has core num=2
Chain[7] ASIC[55] has core num=1
Chain[7] ASIC[57] has core num=2
Check chain[7] PIC fw version=0x03
get PIC voltage=108 on chain[5], value=880
get PIC voltage=74 on chain[6], value=900
get PIC voltage=108 on chain[7], value=880
set_reset_allhashboard = 0x00000000
chain[5] temp offset record: 62,0,0,0,0,0,35,28
chain[5] temp chip I2C addr=0x98
chain[5] has no middle temp, use special fix mode.
chain[6] temp offset record: 62,0,0,0,0,0,35,28
chain[6] temp chip I2C addr=0x98
chain[6] has no middle temp, use special fix mode.
chain[7] temp offset record: 62,0,0,0,0,0,35,28
chain[7] temp chip I2C addr=0x98
chain[7] has no middle temp, use special fix mode.
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
CRC error counter=0
set command mode to VIL
--- check asic number
After Get ASIC NUM CRC error counter=0
set_baud=0
The min freq=700
set real timeout 52, need sleep=379392
After TEST CRC error counter=0
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
search freq for 1 times, completed chain = 3, total chain num = 3
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
restart Miner chance num=2
waiting for receive_func to exit!
waiting for pic heart to exit!
bmminer not found= 1643 root 0:00 grep bmminer
bmminer not found, restart bmminer ...
This is user mode for mining
Detect 1GB control board of XILINX
Miner Type = S9
Miner compile time: Fri Nov 17 17:57:49 CST 2017 type: Antminer S9set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
set_reset_allhashboard = 0x0000ffff
miner ID : 8118b4c610358854
set_reset_allhashboard = 0x0000ffff
Checking fans!get fan[2] speed=6120
get fan[2] speed=6120
get fan[2] speed=6120
get fan[2] speed=6120
get fan[2] speed=6120
get fan[2] speed=6120
get fan[5] speed=13440
get fan[2] speed=6120
get fan[5] speed=13440
get fan[2] speed=6120
get fan[5] speed=13440
chain[5]: [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255]
Chain[J6] has backup chain_voltage=880
Chain[J6] test patten OK temp=-126
Check chain[5] PIC fw version=0x03
chain[6]: [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255]
Chain[J7] has backup chain_voltage=900
Chain[J7] test patten OK temp=-120
Check chain[6] PIC fw version=0x03
chain[7]: [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255]
Chain[J8] has backup chain_voltage=880
Chain[J8] test patten OK temp=-125
Check chain[7] PIC fw version=0x03
Chain[J6] orignal chain_voltage_pic=108 value=880
Chain[J7] orignal chain_voltage_pic=74 value=900
Chain[J8] orignal chain_voltage_pic=108 value=880
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
Chain[J6] has 63 asic
Chain[J7] has 63 asic
Chain[J8] has 63 asic
Chain[J6] has core num in PIC
Chain[J6] ASIC[15] has core num=5
Chain[J7] has core num in PIC
Chain[J7] ASIC[17] has core num=8
Chain[J8] has core num in PIC
Chain[J8] ASIC[8] has core num=13
Chain[J8] ASIC[9] has core num=11
Chain[J8] ASIC[13] has core num=11
Chain[J8] ASIC[19] has core num=14
Chain[J8] ASIC[30] has core num=6
Chain[J8] ASIC[32] has core num=1
Chain[J8] ASIC[42] has core num=2
Chain[J8] ASIC[55] has core num=1
Chain[J8] ASIC[57] has core num=2
miner total rate=13999GH/s fixed rate=13500GH/s
read PIC voltage=940 on chain[5]
Chain:5 chipnum=63
Chain[J6] voltage added=0.2V
Chain:5 temp offset=0
Chain:5 base freq=487
Asic[ 0]:618
Asic[ 1]:631 Asic[ 2]:681 Asic[ 3]:618 Asic[ 4]:631 Asic[ 5]:681 Asic[ 6]:618 Asic[ 7]:631 Asic[ 8]:675
Asic[ 9]:618 Asic[10]:631 Asic[11]:681 Asic[12]:631 Asic[13]:637 Asic[14]:606 Asic[15]:487 Asic[16]:637
Asic[17]:675 Asic[18]:618 Asic[19]:637 Asic[20]:675 Asic[21]:631 Asic[22]:650 Asic[23]:687 Asic[24]:631
Asic[25]:537 Asic[26]:687 Asic[27]:631 Asic[28]:587 Asic[29]:687 Asic[30]:612 Asic[31]:650 Asic[32]:687
Asic[33]:631 Asic[34]:650 Asic[35]:687 Asic[36]:631 Asic[37]:662 Asic[38]:693 Asic[39]:631 Asic[40]:662
Asic[41]:662 Asic[42]:543 Asic[43]:668 Asic[44]:693 Asic[45]:568 Asic[46]:675 Asic[47]:700 Asic[48]:631
Asic[49]:568 Asic[50]:700 Asic[51]:631 Asic[52]:625 Asic[53]:700 Asic[54]:631 Asic[55]:675 Asic[56]:662
Asic[57]:631 Asic[58]:662 Asic[59]:687 Asic[60]:631 Asic[61]:681 Asic[62]:700
Chain:5 max freq=700
Chain:5 min freq=487
read PIC voltage=940 on chain[6]
Chain:6 chipnum=63
Chain[J7] voltage added=0.1V
Chain:6 temp offset=0
Chain:6 base freq=687
Asic[ 0]:650
Asic[ 1]:650 Asic[ 2]:650 Asic[ 3]:650 Asic[ 4]:650 Asic[ 5]:650 Asic[ 6]:650 Asic[ 7]:650 Asic[ 8]:650
Asic[ 9]:650 Asic[10]:650 Asic[11]:650 Asic[12]:650 Asic[13]:650 Asic[14]:650 Asic[15]:650 Asic[16]:650
Asic[17]:650 Asic[18]:650 Asic[19]:650 Asic[20]:650 Asic[21]:650 Asic[22]:650 Asic[23]:650 Asic[24]:650
Asic[25]:650 Asic[26]:656 Asic[27]:656 Asic[28]:656 Asic[29]:656 Asic[30]:656 Asic[31]:656 Asic[32]:656
Asic[33]:656 Asic[34]:656 Asic[35]:656 Asic[36]:656 Asic[37]:656 Asic[38]:656 Asic[39]:656 Asic[40]:656
Asic[41]:656 Asic[42]:656 Asic[43]:656 Asic[44]:656 Asic[45]:656 Asic[46]:656 Asic[47]:656 Asic[48]:656
Asic[49]:656 Asic[50]:656 Asic[51]:656 Asic[52]:656 Asic[53]:656 Asic[54]:656 Asic[55]:656 Asic[56]:656
Asic[57]:656 Asic[58]:656 Asic[59]:656 Asic[60]:656 Asic[61]:656 Asic[62]:656
Chain:6 max freq=656
Chain:6 min freq=650
read PIC voltage=940 on chain[7]
Chain:7 chipnum=63
Chain[J8] voltage added=0.2V
Chain:7 temp offset=0
Chain:7 base freq=637
Asic[ 0]:656
Asic[ 1]:656 Asic[ 2]:656 Asic[ 3]:656 Asic[ 4]:656 Asic[ 5]:656 Asic[ 6]:656 Asic[ 7]:656 Asic[ 8]:637
Asic[ 9]:637 Asic[10]:656 Asic[11]:656 Asic[12]:656 Asic[13]:637 Asic[14]:656 Asic[15]:662 Asic[16]:662
Asic[17]:662 Asic[18]:662 Asic[19]:637 Asic[20]:662 Asic[21]:662 Asic[22]:662 Asic[23]:662 Asic[24]:662
Asic[25]:662 Asic[26]:662 Asic[27]:662 Asic[28]:662 Asic[29]:662 Asic[30]:637 Asic[31]:662 Asic[32]:662
Asic[33]:662 Asic[34]:662 Asic[35]:662 Asic[36]:662 Asic[37]:662 Asic[38]:662 Asic[39]:662 Asic[40]:662
Asic[41]:662 Asic[42]:650 Asic[43]:662 Asic[44]:662 Asic[45]:662 Asic[46]:662 Asic[47]:662 Asic[48]:662
Asic[49]:662 Asic[50]:662 Asic[51]:662 Asic[52]:662 Asic[53]:662 Asic[54]:662 Asic[55]:650 Asic[56]:662
Asic[57]:650 Asic[58]:662 Asic[59]:662 Asic[60]:662 Asic[61]:662 Asic[62]:662
Chain:7 max freq=662
Chain:7 min freq=637
Miner fix freq ...
read PIC voltage=940 on chain[5]
Chain:5 chipnum=63
Chain[J6] voltage added=0.2V
Chain:5 temp offset=0
Chain:5 base freq=487
Asic[ 0]:618
Asic[ 1]:631 Asic[ 2]:650 Asic[ 3]:618 Asic[ 4]:631 Asic[ 5]:656 Asic[ 6]:618 Asic[ 7]:631 Asic[ 8]:656
Asic[ 9]:618 Asic[10]:631 Asic[11]:656 Asic[12]:631 Asic[13]:637 Asic[14]:606 Asic[15]:487 Asic[16]:637
Asic[17]:656 Asic[18]:618 Asic[19]:637 Asic[20]:656 Asic[21]:631 Asic[22]:650 Asic[23]:656 Asic[24]:631
Asic[25]:537 Asic[26]:656 Asic[27]:631 Asic[28]:587 Asic[29]:656 Asic[30]:612 Asic[31]:650 Asic[32]:656
Asic[33]:631 Asic[34]:650 Asic[35]:656 Asic[36]:631 Asic[37]:656 Asic[38]:656 Asic[39]:631 Asic[40]:656
Asic[41]:656 Asic[42]:543 Asic[43]:656 Asic[44]:656 Asic[45]:568 Asic[46]:656 Asic[47]:656 Asic[48]:631
Asic[49]:568 Asic[50]:656 Asic[51]:631 Asic[52]:625 Asic[53]:656 Asic[54]:631 Asic[55]:656 Asic[56]:656
Asic[57]:631 Asic[58]:656 Asic[59]:656 Asic[60]:631 Asic[61]:656 Asic[62]:656
Chain:5 max freq=656
Chain:5 min freq=487
read PIC voltage=940 on chain[6]
Chain:6 chipnum=63
Chain[J7] voltage added=0.1V
Chain:6 temp offset=0
Chain:6 base freq=687
Asic[ 0]:631
Asic[ 1]:631 Asic[ 2]:631 Asic[ 3]:631 Asic[ 4]:631 Asic[ 5]:631 Asic[ 6]:631 Asic[ 7]:631 Asic[ 8]:631
Asic[ 9]:631 Asic[10]:631 Asic[11]:631 Asic[12]:631 Asic[13]:631 Asic[14]:631 Asic[15]:631 Asic[16]:631
Asic[17]:631 Asic[18]:631 Asic[19]:631 Asic[20]:631 Asic[21]:631 Asic[22]:631 Asic[23]:631 Asic[24]:631
Asic[25]:631 Asic[26]:631 Asic[27]:631 Asic[28]:631 Asic[29]:631 Asic[30]:631 Asic[31]:631 Asic[32]:631
Asic[33]:631 Asic[34]:631 Asic[35]:637 Asic[36]:637 Asic[37]:637 Asic[38]:637 Asic[39]:637 Asic[40]:637
Asic[41]:637 Asic[42]:637 Asic[43]:637 Asic[44]:637 Asic[45]:637 Asic[46]:637 Asic[47]:637 Asic[48]:637
Asic[49]:637 Asic[50]:637 Asic[51]:637 Asic[52]:637 Asic[53]:637 Asic[54]:637 Asic[55]:637 Asic[56]:637
Asic[57]:637 Asic[58]:637 Asic[59]:637 Asic[60]:637 Asic[61]:637 Asic[62]:637
Chain:6 max freq=637
Chain:6 min freq=631
read PIC voltage=940 on chain[7]
Chain:7 chipnum=63
Chain[J8] voltage added=0.2V
Chain:7 temp offset=0
Chain:7 base freq=637
Asic[ 0]:637
Asic[ 1]:637 Asic[ 2]:637 Asic[ 3]:637 Asic[ 4]:637 Asic[ 5]:637 Asic[ 6]:637 Asic[ 7]:637 Asic[ 8]:637
Asic[ 9]:637 Asic[10]:637 Asic[11]:637 Asic[12]:637 Asic[13]:637 Asic[14]:637 Asic[15]:637 Asic[16]:637
Asic[17]:637 Asic[18]:637 Asic[19]:637 Asic[20]:637 Asic[21]:637 Asic[22]:637 Asic[23]:637 Asic[24]:637
Asic[25]:637 Asic[26]:637 Asic[27]:637 Asic[28]:637 Asic[29]:637 Asic[30]:637 Asic[31]:637 Asic[32]:637
Asic[33]:637 Asic[34]:637 Asic[35]:637 Asic[36]:637 Asic[37]:637 Asic[38]:637 Asic[39]:637 Asic[40]:637
Asic[41]:637 Asic[42]:637 Asic[43]:637 Asic[44]:637 Asic[45]:637 Asic[46]:637 Asic[47]:637 Asic[48]:637
Asic[49]:643 Asic[50]:643 Asic[51]:643 Asic[52]:643 Asic[53]:643 Asic[54]:643 Asic[55]:643 Asic[56]:643
Asic[57]:643 Asic[58]:643 Asic[59]:643 Asic[60]:643 Asic[61]:643 Asic[62]:643
Chain:7 max freq=643
Chain:7 min freq=637
max freq = 656
set baud=1
Chain[J6] PIC temp offset=62,0,0,0,0,0,35,28
chain[5] temp chip I2C addr=0x98
chain[5] has no middle temp, use special fix mode.
Chain[J6] chip[244] use PIC middle temp offset=0 typeID=55
New offset Chain[5] chip[244] local:26 remote:27 offset:29
Chain[J6] chip[244] get middle temp offset=29 typeID=55
Chain[J7] PIC temp offset=62,0,0,0,0,0,35,28
chain[6] temp chip I2C addr=0x98
chain[6] has no middle temp, use special fix mode.
Chain[J7] chip[244] use PIC middle temp offset=0 typeID=55
New offset Chain[6] chip[244] local:26 remote:27 offset:29
Chain[J7] chip[244] get middle temp offset=29 typeID=55
Chain[J8] PIC temp offset=62,0,0,0,0,0,35,28
chain[7] temp chip I2C addr=0x98
chain[7] has no middle temp, use special fix mode.
Chain[J8] chip[244] use PIC middle temp offset=0 typeID=55
New offset Chain[7] chip[244] local:26 remote:28 offset:28
Chain[J8] chip[244] get middle temp offset=28 typeID=55
miner rate=13501 voltage limit=900 on chain[5]
get PIC voltage=880 on chain[5], check: must be < 900
miner rate=13501 voltage limit=900 on chain[6]
get PIC voltage=900 on chain[6], check: must be < 900
miner rate=13501 voltage limit=900 on chain[7]
get PIC voltage=880 on chain[7], check: must be < 900
Chain[J6] set working voltage=880 [108]
Chain[J7] set working voltage=900 [74]
Chain[J8] set working voltage=880 [108]
do heat board 8xPatten for 1 times
start send works on chain[5]
start send works on chain[6]
start send works on chain[7]
get send work num :57456 on Chain[5]
get send work num :57456 on Chain[6]
get send work num :57456 on Chain[7]
wait recv nonce on chain[5]
wait recv nonce on chain[6]
wait recv nonce on chain[7]
get nonces on chain[5]
require nonce number:912
require validnonce number:57456
asic[00]=912 asic[01]=912 asic[02]=912 asic[03]=912 asic[04]=912 asic[05]=912 asic[06]=912 asic[07]=912
asic[08]=912 asic[09]=912 asic[10]=912 asic[11]=912 asic[12]=912 asic[13]=912 asic[14]=912 asic[15]=912
asic[16]=912 asic[17]=912 asic[18]=912 asic[19]=912 asic[20]=912 asic[21]=912 asic[22]=912 asic[23]=912
asic[24]=912 asic[25]=912 asic[26]=912 asic[27]=912 asic[28]=912 asic[29]=912 asic[30]=912 asic[31]=912
asic[32]=912 asic[33]=912 asic[34]=912 asic[35]=912 asic[36]=912 asic[37]=912 asic[38]=912 asic[39]=912
asic[40]=912 asic[41]=912 asic[42]=912 asic[43]=912 asic[44]=912 asic[45]=912 asic[46]=912 asic[47]=912
asic[48]=912 asic[49]=912 asic[50]=912 asic[51]=912 asic[52]=912 asic[53]=912 asic[54]=912 asic[55]=912
asic[56]=912 asic[57]=912 asic[58]=912 asic[59]=912 asic[60]=912 asic[61]=912 asic[62]=912
Below ASIC's core didn't receive all the nonce, they should receive 8 nonce each!
freq[00]=618 freq[01]=631 freq[02]=650 freq[03]=618 freq[04]=631 freq[05]=656 freq[06]=618 freq[07]=631
freq[08]=656 freq[09]=618 freq[10]=631 freq[11]=656 freq[12]=631 freq[13]=637 freq[14]=606 freq[15]=487
freq[16]=637 freq[17]=656 freq[18]=618 freq[19]=637 freq[20]=656 freq[21]=631 freq[22]=650 freq[23]=656
freq[24]=631 freq[25]=537 freq[26]=656 freq[27]=631 freq[28]=587 freq[29]=656 freq[30]=612 freq[31]=650
freq[32]=656 freq[33]=631 freq[34]=650 freq[35]=656 freq[36]=631 freq[37]=656 freq[38]=656 freq[39]=631
freq[40]=656 freq[41]=656 freq[42]=543 freq[43]=656 freq[44]=656 freq[45]=568 freq[46]=656 freq[47]=656
freq[48]=631 freq[49]=568 freq[50]=656 freq[51]=631 freq[52]=625 freq[53]=656 freq[54]=631 freq[55]=656
freq[56]=656 freq[57]=631 freq[58]=656 freq[59]=656 freq[60]=631 freq[61]=656 freq[62]=656
total valid nonce number:57456
total send work number:57456
require valid nonce number:57456
repeated_nonce_num:0
err_nonce_num:25912
last_nonce_num:14370
get nonces on chain[6]
require nonce number:912
require validnonce number:57456
asic[00]=912 asic[01]=912 asic[02]=912 asic[03]=912 asic[04]=912 asic[05]=912 asic[06]=912 asic[07]=912
asic[08]=912 asic[09]=912 asic[10]=912 asic[11]=912 asic[12]=912 asic[13]=912 asic[14]=912 asic[15]=912
asic[16]=912 asic[17]=912 asic[18]=912 asic[19]=912 asic[20]=912 asic[21]=912 asic[22]=912 asic[23]=912
asic[24]=912 asic[25]=912 asic[26]=912 asic[27]=912 asic[28]=912 asic[29]=912 asic[30]=912 asic[31]=912
asic[32]=912 asic[33]=912 asic[34]=912 asic[35]=912 asic[36]=912 asic[37]=912 asic[38]=912 asic[39]=912
asic[40]=912 asic[41]=912 asic[42]=912 asic[43]=912 asic[44]=912 asic[45]=912 asic[46]=912 asic[47]=912
asic[48]=912 asic[49]=912 asic[50]=912 asic[51]=912 asic[52]=912 asic[53]=912 asic[54]=912 asic[55]=912
asic[56]=912 asic[57]=912 asic[58]=912 asic[59]=912 asic[60]=912 asic[61]=912 asic[62]=912
Below ASIC's core didn't receive all the nonce, they should receive 8 nonce each!
freq[00]=631 freq[01]=631 freq[02]=631 freq[03]=631 freq[04]=631 freq[05]=631 freq[06]=631 freq[07]=631
freq[08]=631 freq[09]=631 freq[10]=631 freq[11]=631 freq[12]=631 freq[13]=631 freq[14]=631 freq[15]=631
freq[16]=631 freq[17]=631 freq[18]=631 freq[19]=631 freq[20]=631 freq[21]=631 freq[22]=631 freq[23]=631
freq[24]=631 freq[25]=631 freq[26]=631 freq[27]=631 freq[28]=631 freq[29]=631 freq[30]=631 freq[31]=631
freq[32]=631 freq[33]=631 freq[34]=631 freq[35]=637 freq[36]=637 freq[37]=637 freq[38]=637 freq[39]=637
freq[40]=637 freq[41]=637 freq[42]=637 freq[43]=637 freq[44]=637 freq[45]=637 freq[46]=637 freq[47]=637
freq[48]=637 freq[49]=637 freq[50]=637 freq[51]=637 freq[52]=637 freq[53]=637 freq[54]=637 freq[55]=637
freq[56]=637 freq[57]=637 freq[58]=637 freq[59]=637 freq[60]=637 freq[61]=637 freq[62]=637
total valid nonce number:57456
total send work number:57456
require valid nonce number:57456
repeated_nonce_num:0
err_nonce_num:25987
last_nonce_num:14368
get nonces on chain[7]
require nonce number:912
require validnonce number:57456
asic[00]=912 asic[01]=912 asic[02]=912 asic[03]=912 asic[04]=912 asic[05]=912 asic[06]=912 asic[07]=912
asic[08]=907 asic[09]=912 asic[10]=912 asic[11]=912 asic[12]=912 asic[13]=912 asic[14]=912 asic[15]=912
asic[16]=912 asic[17]=912 asic[18]=912 asic[19]=909 asic[20]=912 asic[21]=912 asic[22]=912 asic[23]=912
asic[24]=912 asic[25]=912 asic[26]=912 asic[27]=912 asic[28]=912 asic[29]=912 asic[30]=912 asic[31]=912
asic[32]=912 asic[33]=912 asic[34]=912 asic[35]=912 asic[36]=912 asic[37]=912 asic[38]=912 asic[39]=912
asic[40]=912 asic[41]=912 asic[42]=912 asic[43]=912 asic[44]=912 asic[45]=912 asic[46]=912 asic[47]=912
asic[48]=912 asic[49]=912 asic[50]=912 asic[51]=912 asic[52]=912 asic[53]=912 asic[54]=912 asic[55]=911
asic[56]=912 asic[57]=912 asic[58]=912 asic[59]=912 asic[60]=912 asic[61]=912 asic[62]=912
Below ASIC's core didn't receive all the nonce, they should receive 8 nonce each!
asic[08]=907
core[049]=7 core[053]=5 core[056]=7
asic[19]=909
core[064]=7 core[112]=6
asic[55]=911
core[007]=7
freq[00]=637 freq[01]=637 freq[02]=637 freq[03]=637 freq[04]=637 freq[05]=637 freq[06]=637 freq[07]=637
freq[08]=637 freq[09]=637 freq[10]=637 freq[11]=637 freq[12]=637 freq[13]=637 freq[14]=637 freq[15]=637
freq[16]=637 freq[17]=637 freq[18]=637 freq[19]=637 freq[20]=637 freq[21]=637 freq[22]=637 freq[23]=637
freq[24]=637 freq[25]=637 freq[26]=637 freq[27]=637 freq[28]=637 freq[29]=637 freq[30]=637 freq[31]=637
freq[32]=637 freq[33]=637 freq[34]=637 freq[35]=637 freq[36]=637 freq[37]=637 freq[38]=637 freq[39]=637
freq[40]=637 freq[41]=637 freq[42]=637 freq[43]=637 freq[44]=637 freq[45]=637 freq[46]=637 freq[47]=637
freq[48]=637 freq[49]=643 freq[50]=643 freq[51]=643 freq[52]=643 freq[53]=643 freq[54]=643 freq[55]=643
freq[56]=643 freq[57]=643 freq[58]=643 freq[59]=643 freq[60]=643 freq[61]=643 freq[62]=643
total valid nonce number:57447
total send work number:57456
require valid nonce number:57456
repeated_nonce_num:0
err_nonce_num:26183
last_nonce_num:35748
chain[5]: All chip cores are opened OK!
Test Patten on chain[5]: OK!
chain[6]: All chip cores are opened OK!
Test Patten on chain[6]: OK!
chain[7]: All chip cores are opened OK!
Test Patten on chain[7]: OK!
setStartTimePoint total_tv_start_sys=217 total_tv_end_sys=218
restartNum = 2 , auto-reinit enabled...
do read_temp_func once...
do check_asic_reg 0x08
get RT hashrate from Chain[5]: (asic index start from 1-63)
Asic[01]=72.5110 Asic[02]=68.6020 Asic[03]=74.4230 Asic[04]=74.6750 Asic[05]=71.4540 Asic[06]=77.5610 Asic[07]=74.7760 Asic[08]=74.3900
Asic[09]=77.7790 Asic[10]=76.7220 Asic[11]=73.8020 Asic[12]=68.5850 Asic[13]=76.1680 Asic[14]=72.4770 Asic[15]=73.0470 Asic[16]=57.8810
Asic[17]=74.4740 Asic[18]=76.4530 Asic[19]=67.8800 Asic[20]=70.1280 Asic[21]=73.7520 Asic[22]=74.6580 Asic[23]=73.6850 Asic[24]=78.5170
Asic[25]=73.6850 Asic[26]=63.6860 Asic[27]=80.9660 Asic[28]=73.9200 Asic[29]=68.9870 Asic[30]=75.6310 Asic[31]=74.9770 Asic[32]=69.4570
Asic[33]=74.6580 Asic[34]=79.8930 Asic[35]=76.6710 Asic[36]=74.3730 Asic[37]=66.6050 Asic[38]=76.7380 Asic[39]=71.4540 Asic[40]=69.3060
Asic[41]=72.5610 Asic[42]=73.8530 Asic[43]=58.9210 Asic[44]=75.3800 Asic[45]=73.1310 Asic[46]=68.4000 Asic[47]=77.6780 Asic[48]=73.1150
Asic[49]=69.2890 Asic[50]=62.8130 Asic[51]=74.2720 Asic[52]=73.1480 Asic[53]=67.4440 Asic[54]=72.4940 Asic[55]=68.1990 Asic[56]=72.4100
Asic[57]=75.3460 Asic[58]=66.1350 Asic[59]=72.9800 Asic[60]=78.1480 Asic[61]=72.3260 Asic[62]=72.5610 Asic[63]=77.7950
get RT hashrate from Chain[6]: (asic index start from 1-63)
Asic[01]=67.6620 Asic[02]=75.9840 Asic[03]=70.3300 Asic[04]=75.5640 Asic[05]=62.8470 Asic[06]=70.2790 Asic[07]=74.5240 Asic[08]=72.9130
Asic[09]=70.6320 Asic[10]=72.5610 Asic[11]=73.9370 Asic[12]=77.3420 Asic[13]=72.4440 Asic[14]=68.8030 Asic[15]=73.0810 Asic[16]=73.8360
Asic[17]=73.5510 Asic[18]=73.9700 Asic[19]=71.0340 Asic[20]=71.1680 Asic[21]=72.1580 Asic[22]=78.8190 Asic[23]=71.9230 Asic[24]=69.4570
Asic[25]=67.7630 Asic[26]=71.7220 Asic[27]=76.4030 Asic[28]=71.1180 Asic[29]=68.7360 Asic[30]=69.7090 Asic[31]=77.5610 Asic[32]=70.1790
Asic[33]=67.9140 Asic[34]=72.3930 Asic[35]=64.5920 Asic[36]=72.1920 Asic[37]=74.6080 Asic[38]=75.4470 Asic[39]=73.8700 Asic[40]=73.9370
Asic[41]=66.2860 Asic[42]=79.4230 Asic[43]=75.8160 Asic[44]=68.6350 Asic[45]=74.7920 Asic[46]=70.7990 Asic[47]=71.2360 Asic[48]=73.8700
Asic[49]=66.5380 Asic[50]=70.6150 Asic[51]=72.6280 Asic[52]=75.7490 Asic[53]=71.8400 Asic[54]=76.5370 Asic[55]=73.5340 Asic[56]=69.2390
Asic[57]=75.1280 Asic[58]=74.3230 Asic[59]=73.4330 Asic[60]=72.3430 Asic[61]=77.6780 Asic[62]=82.4600 Asic[63]=69.5240
get RT hashrate from Chain[7]: (asic index start from 1-63)
Asic[01]=73.5510 Asic[02]=75.9160 Asic[03]=80.1110 Asic[04]=76.9900 Asic[05]=76.1510 Asic[06]=73.5170 Asic[07]=74.9940 Asic[08]=73.1150
Asic[09]=70.6650 Asic[10]=70.6990 Asic[11]=72.4770 Asic[12]=70.1450 Asic[13]=74.3060 Asic[14]=71.8060 Asic[15]=74.7420 Asic[16]=75.6650
Asic[17]=76.8220 Asic[18]=69.5240 Asic[19]=72.0910 Asic[20]=75.2620 Asic[21]=72.0240 Asic[22]=73.2660 Asic[23]=76.2690 Asic[24]=69.9440
Asic[25]=67.7290 Asic[26]=71.7050 Asic[27]=74.6250 Asic[28]=78.2320 Asic[29]=69.8430 Asic[30]=68.4670 Asic[31]=71.5210 Asic[32]=68.9540
Asic[33]=74.6250 Asic[34]=71.8730 Asic[35]=74.4400 Asic[36]=74.8760 Asic[37]=73.9030 Asic[38]=72.9300 Asic[39]=69.6250 Asic[40]=74.9430
Asic[41]=72.7620 Asic[42]=69.4910 Asic[43]=67.4270 Asic[44]=71.4870 Asic[45]=74.4570 Asic[46]=66.6550 Asic[47]=67.5450 Asic[48]=75.4800
Asic[49]=72.2590 Asic[50]=72.9300 Asic[51]=75.6820 Asic[52]=71.9070 Asic[53]=67.9640 Asic[54]=67.8470 Asic[55]=74.3900 Asic[56]=71.0010
Asic[57]=75.8490 Asic[58]=74.9270 Asic[59]=72.3930 Asic[60]=74.3730 Asic[61]=75.5310 Asic[62]=73.8190 Asic[63]=72.4440
Check Chain[J6] ASIC RT error: (asic index start from 1-63)
Check Chain[J7] ASIC RT error: (asic index start from 1-63)
Check Chain[J8] ASIC RT error: (asic index start from 1-63)
Done check_asic_reg
do read temp on Chain[5]
Chain[5] Chip[62] TempTypeID=55 middle offset=29
Chain[5] Chip[62] local Temp=60
Chain[5] Chip[62] middle Temp=70
Special fix Chain[5] Chip[62] middle Temp = 75
Done read temp on Chain[5]
do read temp on Chain[6]
Chain[6] Chip[62] TempTypeID=55 middle offset=29
Chain[6] Chip[62] local Temp=60
Chain[6] Chip[62] middle Temp=72
Special fix Chain[6] Chip[62] middle Temp = 75
Done read temp on Chain[6]
do read temp on Chain[7]
Chain[7] Chip[62] TempTypeID=55 middle offset=28
Chain[7] Chip[62] local Temp=62
Chain[7] Chip[62] middle Temp=72
Special fix Chain[7] Chip[62] middle Temp = 77
Done read temp on Chain[7]
set FAN speed according to: temp_highest=62 temp_top1[PWM_T]=62 temp_top1[TEMP_POS_LOCAL]=62 temp_change=0 fix_fan_steps=0
FAN PWM: 74
read_temp_func Done!
CRC error counter=0
submitted by Timsierramist to BitcoinMining [link] [comments]

Antminer S9 not hashing?

Good morning folks,
I have an Antminer S9 that has performed flawlessly. After I moved it to a better location, I noticed that it no longer seems to be working. The green light is flashing, but it doesn't seem to be hashing to my pool (Nicehash).
I'm fairly new to Bitcoining mining and can't make sense of some of the information on my status screen. Before I jump into Bitmain support, I was wondering if anyone could clue me in as to what the problem might be.
https://s15.postimg.cc/i0n5qsyoInked_Capture_LI.jpg
I'll post my Kernal Log here.
Thank you in advance!!!
KERNAL LOG: [ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 3.14.0-xilinx-ge8a2f71-dirty ([email protected]) (gcc version 4.8.3 20140320 (prerelease) (Sourcery CodeBench Lite 2014.05-23) ) #82 SMP PREEMPT Tue May 16 19:49:53 CST 2017
[ 0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Machine model: Xilinx Zynq
[ 0.000000] cma: CMA: reserved 128 MiB at 27800000
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] On node 0 totalpages: 258048
[ 0.000000] free_area_init_node: node 0, pgdat c0740a40, node_mem_map e6fd8000
[ 0.000000] Normal zone: 1520 pages used for memmap
[ 0.000000] Normal zone: 0 pages reserved
[ 0.000000] Normal zone: 194560 pages, LIFO batch:31
[ 0.000000] HighMem zone: 496 pages used for memmap
[ 0.000000] HighMem zone: 63488 pages, LIFO batch:15
[ 0.000000] PERCPU: Embedded 8 pages/cpu @e6fc0000 s9088 r8192 d15488 u32768
[ 0.000000] pcpu-alloc: s9088 r8192 d15488 u32768 alloc=8*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 256528
[ 0.000000] Kernel command line: noinitrd mem=1008M console=ttyPS0,115200 root=ubi0:rootfs ubi.mtd=1 rootfstype=ubifs rw rootwait
[ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Memory: 884148K/1032192K available (5032K kernel code, 283K rwdata, 1916K rodata, 204K init, 258K bss, 148044K reserved, 253952K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xf0000000 - 0xff000000 ( 240 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xef800000 ( 760 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc06d1374 (6949 kB)
[ 0.000000] .init : 0xc06d2000 - 0xc0705380 ( 205 kB)
[ 0.000000] .data : 0xc0706000 - 0xc074cf78 ( 284 kB)
[ 0.000000] .bss : 0xc074cf84 - 0xc078d9fc ( 259 kB)
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] Dump stacks of tasks blocking RCU-preempt GP.
[ 0.000000] RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] ps7-slcr mapped to f0004000
[ 0.000000] zynq_clock_init: clkc starts at f0004100
[ 0.000000] Zynq clock init
[ 0.000015] sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 3298534883328ns
[ 0.000308] ps7-ttc #0 at f0006000, irq=43
[ 0.000618] Console: colour dummy device 80x30
[ 0.000658] Calibrating delay loop... 1325.46 BogoMIPS (lpj=6627328)
[ 0.040207] pid_max: default: 32768 minimum: 301
[ 0.040436] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.040459] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.042612] CPU: Testing write buffer coherency: ok
[ 0.042974] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.043036] Setting up static identity map for 0x4c4b00 - 0x4c4b58
[ 0.043263] L310 cache controller enabled
[ 0.043282] l2x0: 8 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x72760000, Cache size: 512 kB
[ 0.121037] CPU1: Booted secondary processor
[ 0.210227] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.210357] Brought up 2 CPUs
[ 0.210376] SMP: Total of 2 processors activated.
[ 0.210385] CPU: All CPU(s) started in SVC mode.
[ 0.211051] devtmpfs: initialized
[ 0.213481] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
[ 0.214724] regulator-dummy: no parameters
[ 0.223736] NET: Registered protocol family 16
[ 0.226067] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.228361] cpuidle: using governor ladder
[ 0.228374] cpuidle: using governor menu
[ 0.235908] syscon f8000000.ps7-slcr: regmap [mem 0xf8000000-0xf8000fff] registered
[ 0.237440] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
[ 0.237453] hw-breakpoint: maximum watchpoint size is 4 bytes.
[ 0.237572] zynq-ocm f800c000.ps7-ocmc: ZYNQ OCM pool: 256 KiB @ 0xf0080000
[ 0.259435] bio: create slab at 0
[ 0.261172] vgaarb: loaded
[ 0.261915] SCSI subsystem initialized
[ 0.262814] usbcore: registered new interface driver usbfs
[ 0.262985] usbcore: registered new interface driver hub
[ 0.263217] usbcore: registered new device driver usb
[ 0.263743] media: Linux media interface: v0.10
[ 0.263902] Linux video capture interface: v2.00
[ 0.264150] pps_core: LinuxPPS API ver. 1 registered
[ 0.264162] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <[[email protected]](mailto:[email protected])>
[ 0.264286] PTP clock support registered
[ 0.264656] EDAC MC: Ver: 3.0.0
[ 0.265719] Advanced Linux Sound Architecture Driver Initialized.
[ 0.268708] DMA-API: preallocated 4096 debug entries
[ 0.268724] DMA-API: debugging enabled by kernel config
[ 0.268820] Switched to clocksource arm_global_timer
[ 0.289596] NET: Registered protocol family 2
[ 0.290280] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.290375] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[ 0.290535] TCP: Hash tables configured (established 8192 bind 8192)
[ 0.290612] TCP: reno registered
[ 0.290633] UDP hash table entries: 512 (order: 2, 16384 bytes)
[ 0.290689] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[ 0.290971] NET: Registered protocol family 1
[ 0.291346] RPC: Registered named UNIX socket transport module.
[ 0.291359] RPC: Registered udp transport module.
[ 0.291368] RPC: Registered tcp transport module.
[ 0.291376] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.291391] PCI: CLS 0 bytes, default 64
[ 0.291857] hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
[ 0.293945] futex hash table entries: 512 (order: 3, 32768 bytes)
[ 0.295408] bounce pool size: 64 pages
[ 0.296323] jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
[ 0.296525] msgmni has been set to 1486
[ 0.297330] io scheduler noop registered
[ 0.297343] io scheduler deadline registered
[ 0.297385] io scheduler cfq registered (default)
[ 0.308358] dma-pl330 f8003000.ps7-dma: Loaded driver for PL330 DMAC-2364208
[ 0.308380] dma-pl330 f8003000.ps7-dma: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
[ 0.434378] e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 82, base_baud = 3124999) is a xuartps
[ 1.006815] console [ttyPS0] enabled
[ 1.011106] xdevcfg f8007000.ps7-dev-cfg: ioremap 0xf8007000 to f0068000
[ 1.018731] [drm] Initialized drm 1.1.0 20060810
[ 1.036029] brd: module loaded
[ 1.045494] loop: module loaded
[ 1.055163] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 1.060985] e1000e: Copyright(c) 1999 - 2013 Intel Corporation.
[ 1.068779] libphy: XEMACPS mii bus: probed
[ 1.073341] ------------- phy_id = 0x3625e62
[ 1.078112] xemacps e000b000.ps7-ethernet: pdev->id -1, baseaddr 0xe000b000, irq 54
[ 1.087072] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 1.093912] ehci-pci: EHCI PCI platform driver
[ 1.101155] zynq-dr e0002000.ps7-usb: Unable to init USB phy, missing?
[ 1.107952] usbcore: registered new interface driver usb-storage
[ 1.114850] mousedev: PS/2 mouse device common for all mice
[ 1.120975] i2c /dev entries driver
[ 1.127946] zynq-edac f8006000.ps7-ddrc: ecc not enabled
[ 1.133474] cpufreq_cpu0: failed to get cpu0 regulator: -19
[ 1.139426] Xilinx Zynq CpuIdle Driver started
[ 1.144261] sdhci: Secure Digital Host Controller Interface driver
[ 1.150384] sdhci: Copyright(c) Pierre Ossman
[ 1.154700] sdhci-pltfm: SDHCI platform and OF driver helper
[ 1.161601] mmc0: no vqmmc regulator found
[ 1.165614] mmc0: no vmmc regulator found
[ 1.208845] mmc0: SDHCI controller on e0100000.ps7-sdio [e0100000.ps7-sdio] using ADMA
[ 1.217539] usbcore: registered new interface driver usbhid
[ 1.223054] usbhid: USB HID core driver
[ 1.227806] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda
[ 1.234107] nand: Micron MT29F2G08ABAEAWP
[ 1.238074] nand: 256MiB, SLC, page size: 2048, OOB size: 64
[ 1.244027] Bad block table found at page 131008, version 0x01
[ 1.250251] Bad block table found at page 130944, version 0x01
[ 1.256303] 3 ofpart partitions found on MTD device pl353-nand
[ 1.262080] Creating 3 MTD partitions on "pl353-nand":
[ 1.267174] 0x000000000000-0x000002000000 : "BOOT.bin-env-dts-kernel"
[ 1.275230] 0x000002000000-0x00000b000000 : "angstram-rootfs"
[ 1.282582] 0x00000b000000-0x000010000000 : "upgrade-rootfs"
[ 1.291630] TCP: cubic registered
[ 1.294869] NET: Registered protocol family 17
[ 1.299597] Registering SWP/SWPB emulation handler
[ 1.305497] regulator-dummy: disabling
[ 1.309875] UBI: attaching mtd1 to ubi0
[ 1.836565] UBI: scanning is finished
[ 1.848221] UBI: attached mtd1 (name "angstram-rootfs", size 144 MiB) to ubi0
[ 1.855302] UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
[ 1.862063] UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
[ 1.868728] UBI: VID header offset: 2048 (aligned 2048), data offset: 4096
[ 1.875605] UBI: good PEBs: 1152, bad PEBs: 0, corrupted PEBs: 0
[ 1.881586] UBI: user volume: 1, internal volumes: 1, max. volumes count: 128
[ 1.888693] UBI: max/mean erase counter: 4/1, WL threshold: 4096, image sequence number: 1134783803
[ 1.897736] UBI: available PEBs: 0, total reserved PEBs: 1152, PEBs reserved for bad PEB handling: 40
[ 1.906953] UBI: background thread "ubi_bgt0d" started, PID 1080
[ 1.906959] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[ 1.911038] ALSA device list:
[ 1.911042] No soundcards found.
[ 1.927420] UBIFS: background thread "ubifs_bgt0_0" started, PID 1082
[ 1.956473] UBIFS: recovery needed
[ 2.016970] UBIFS: recovery completed
[ 2.020709] UBIFS: mounted UBI device 0, volume 0, name "rootfs"
[ 2.026635] UBIFS: LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes
[ 2.035771] UBIFS: FS size: 128626688 bytes (122 MiB, 1013 LEBs), journal size 9023488 bytes (8 MiB, 72 LEBs)
[ 2.045653] UBIFS: reserved for root: 0 bytes (0 KiB)
[ 2.050693] UBIFS: media format: w4/r0 (latest is w4/r0), UUID B079DD56-06BB-4E31-8F5E-A6604F480DB2, small LPT model
[ 2.061987] VFS: Mounted root (ubifs filesystem) on device 0:11.
[ 2.069184] devtmpfs: mounted
[ 2.072297] Freeing unused kernel memory: 204K (c06d2000 - c0705000)
[ 2.920928] random: dd urandom read with 0 bits of entropy available
[ 3.318860]
[ 3.318860] bcm54xx_config_init
[ 3.928853]
[ 3.928853] bcm54xx_config_init
[ 7.929682] xemacps e000b000.ps7-ethernet: Set clk to 124999998 Hz
[ 7.935787] xemacps e000b000.ps7-ethernet: link up (1000/FULL)
[ 22.563181] In axi fpga driver!
[ 22.566260] request_mem_region OK!
[ 22.569676] AXI fpga dev virtual address is 0xf01fe000
[ 22.574751] *base_vir_addr = 0x8c510
[ 22.590723] In fpga mem driver!
[ 22.593791] request_mem_region OK!
[ 22.597361] fpga mem virtual address is 0xf3000000
[ 23.408156]
[ 23.408156] bcm54xx_config_init
[ 24.038071]
[ 24.038071] bcm54xx_config_init
[ 28.038487] xemacps e000b000.ps7-ethernet: Set clk to 124999998 Hz
[ 28.044593] xemacps e000b000.ps7-ethernet: link up (1000/FULL)
This is XILINX board. Totalram: 1039794176
Detect 1GB control board of XILINX
DETECT HW version=0008c510
miner ID : 8118b4c610358854
Miner Type = S9
AsicType = 1387
real AsicNum = 63
use critical mode to search freq...
get PLUG ON=0x000000e0
Find hashboard on Chain[5]
Find hashboard on Chain[6]
Find hashboard on Chain[7]
set_reset_allhashboard = 0x0000ffff
Check chain[5] PIC fw version=0x03
Check chain[6] PIC fw version=0x03
Check chain[7] PIC fw version=0x03
chain[5]: [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255]
has freq in PIC, will disable freq setting.
chain[5] has freq in PIC and will jump over...
Chain[5] has core num in PIC
Chain[5] ASIC[15] has core num=5
Check chain[5] PIC fw version=0x03
chain[6]: [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255]
has freq in PIC, will disable freq setting.
chain[6] has freq in PIC and will jump over...
Chain[6] has core num in PIC
Chain[6] ASIC[17] has core num=8
Check chain[6] PIC fw version=0x03
chain[7]: [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255]
has freq in PIC, will disable freq setting.
chain[7] has freq in PIC and will jump over...
Chain[7] has core num in PIC
Chain[7] ASIC[8] has core num=13
Chain[7] ASIC[9] has core num=11
Chain[7] ASIC[13] has core num=11
Chain[7] ASIC[19] has core num=14
Chain[7] ASIC[30] has core num=6
Chain[7] ASIC[32] has core num=1
Chain[7] ASIC[42] has core num=2
Chain[7] ASIC[55] has core num=1
Chain[7] ASIC[57] has core num=2
Check chain[7] PIC fw version=0x03
get PIC voltage=108 on chain[5], value=880
get PIC voltage=74 on chain[6], value=900
get PIC voltage=108 on chain[7], value=880
set_reset_allhashboard = 0x00000000
chain[5] temp offset record: 62,0,0,0,0,0,35,28
chain[5] temp chip I2C addr=0x98
chain[5] has no middle temp, use special fix mode.
chain[6] temp offset record: 62,0,0,0,0,0,35,28
chain[6] temp chip I2C addr=0x98
chain[6] has no middle temp, use special fix mode.
chain[7] temp offset record: 62,0,0,0,0,0,35,28
chain[7] temp chip I2C addr=0x98
chain[7] has no middle temp, use special fix mode.
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
CRC error counter=0
set command mode to VIL
--- check asic number
After Get ASIC NUM CRC error counter=0
set_baud=0
The min freq=700
set real timeout 52, need sleep=379392
After TEST CRC error counter=0
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
search freq for 1 times, completed chain = 3, total chain num = 3
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
restart Miner chance num=2
waiting for receive_func to exit!
waiting for pic heart to exit!
bmminer not found= 1643 root 0:00 grep bmminer
bmminer not found, restart bmminer ...
This is user mode for mining
Detect 1GB control board of XILINX
Miner Type = S9
Miner compile time: Fri Nov 17 17:57:49 CST 2017 type: Antminer S9set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
set_reset_allhashboard = 0x0000ffff
miner ID : 8118b4c610358854
set_reset_allhashboard = 0x0000ffff
Checking fans!get fan[2] speed=6120
get fan[2] speed=6120
get fan[2] speed=6120
get fan[2] speed=6120
get fan[2] speed=6120
get fan[2] speed=6120
get fan[5] speed=13440
get fan[2] speed=6120
get fan[5] speed=13440
get fan[2] speed=6120
get fan[5] speed=13440
chain[5]: [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255]
Chain[J6] has backup chain_voltage=880
Chain[J6] test patten OK temp=-126
Check chain[5] PIC fw version=0x03
chain[6]: [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255]
Chain[J7] has backup chain_voltage=900
Chain[J7] test patten OK temp=-120
Check chain[6] PIC fw version=0x03
chain[7]: [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255] [63:255]
Chain[J8] has backup chain_voltage=880
Chain[J8] test patten OK temp=-125
Check chain[7] PIC fw version=0x03
Chain[J6] orignal chain_voltage_pic=108 value=880
Chain[J7] orignal chain_voltage_pic=74 value=900
Chain[J8] orignal chain_voltage_pic=108 value=880
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
Chain[J6] has 63 asic
Chain[J7] has 63 asic
Chain[J8] has 63 asic
Chain[J6] has core num in PIC
Chain[J6] ASIC[15] has core num=5
Chain[J7] has core num in PIC
Chain[J7] ASIC[17] has core num=8
Chain[J8] has core num in PIC
Chain[J8] ASIC[8] has core num=13
Chain[J8] ASIC[9] has core num=11
Chain[J8] ASIC[13] has core num=11
Chain[J8] ASIC[19] has core num=14
Chain[J8] ASIC[30] has core num=6
Chain[J8] ASIC[32] has core num=1
Chain[J8] ASIC[42] has core num=2
Chain[J8] ASIC[55] has core num=1
Chain[J8] ASIC[57] has core num=2
miner total rate=13999GH/s fixed rate=13500GH/s
read PIC voltage=940 on chain[5]
Chain:5 chipnum=63
Chain[J6] voltage added=0.2V
Chain:5 temp offset=0
Chain:5 base freq=487
Asic[ 0]:618
Asic[ 1]:631 Asic[ 2]:681 Asic[ 3]:618 Asic[ 4]:631 Asic[ 5]:681 Asic[ 6]:618 Asic[ 7]:631 Asic[ 8]:675
Asic[ 9]:618 Asic[10]:631 Asic[11]:681 Asic[12]:631 Asic[13]:637 Asic[14]:606 Asic[15]:487 Asic[16]:637
Asic[17]:675 Asic[18]:618 Asic[19]:637 Asic[20]:675 Asic[21]:631 Asic[22]:650 Asic[23]:687 Asic[24]:631
Asic[25]:537 Asic[26]:687 Asic[27]:631 Asic[28]:587 Asic[29]:687 Asic[30]:612 Asic[31]:650 Asic[32]:687
Asic[33]:631 Asic[34]:650 Asic[35]:687 Asic[36]:631 Asic[37]:662 Asic[38]:693 Asic[39]:631 Asic[40]:662
Asic[41]:662 Asic[42]:543 Asic[43]:668 Asic[44]:693 Asic[45]:568 Asic[46]:675 Asic[47]:700 Asic[48]:631
Asic[49]:568 Asic[50]:700 Asic[51]:631 Asic[52]:625 Asic[53]:700 Asic[54]:631 Asic[55]:675 Asic[56]:662
Asic[57]:631 Asic[58]:662 Asic[59]:687 Asic[60]:631 Asic[61]:681 Asic[62]:700
Chain:5 max freq=700
Chain:5 min freq=487
read PIC voltage=940 on chain[6]
Chain:6 chipnum=63
Chain[J7] voltage added=0.1V
Chain:6 temp offset=0
Chain:6 base freq=687
Asic[ 0]:650
Asic[ 1]:650 Asic[ 2]:650 Asic[ 3]:650 Asic[ 4]:650 Asic[ 5]:650 Asic[ 6]:650 Asic[ 7]:650 Asic[ 8]:650
Asic[ 9]:650 Asic[10]:650 Asic[11]:650 Asic[12]:650 Asic[13]:650 Asic[14]:650 Asic[15]:650 Asic[16]:650
Asic[17]:650 Asic[18]:650 Asic[19]:650 Asic[20]:650 Asic[21]:650 Asic[22]:650 Asic[23]:650 Asic[24]:650
Asic[25]:650 Asic[26]:656 Asic[27]:656 Asic[28]:656 Asic[29]:656 Asic[30]:656 Asic[31]:656 Asic[32]:656
Asic[33]:656 Asic[34]:656 Asic[35]:656 Asic[36]:656 Asic[37]:656 Asic[38]:656 Asic[39]:656 Asic[40]:656
Asic[41]:656 Asic[42]:656 Asic[43]:656 Asic[44]:656 Asic[45]:656 Asic[46]:656 Asic[47]:656 Asic[48]:656
Asic[49]:656 Asic[50]:656 Asic[51]:656 Asic[52]:656 Asic[53]:656 Asic[54]:656 Asic[55]:656 Asic[56]:656
Asic[57]:656 Asic[58]:656 Asic[59]:656 Asic[60]:656 Asic[61]:656 Asic[62]:656
Chain:6 max freq=656
Chain:6 min freq=650
read PIC voltage=940 on chain[7]
Chain:7 chipnum=63
Chain[J8] voltage added=0.2V
Chain:7 temp offset=0
Chain:7 base freq=637
Asic[ 0]:656
Asic[ 1]:656 Asic[ 2]:656 Asic[ 3]:656 Asic[ 4]:656 Asic[ 5]:656 Asic[ 6]:656 Asic[ 7]:656 Asic[ 8]:637
Asic[ 9]:637 Asic[10]:656 Asic[11]:656 Asic[12]:656 Asic[13]:637 Asic[14]:656 Asic[15]:662 Asic[16]:662
Asic[17]:662 Asic[18]:662 Asic[19]:637 Asic[20]:662 Asic[21]:662 Asic[22]:662 Asic[23]:662 Asic[24]:662
Asic[25]:662 Asic[26]:662 Asic[27]:662 Asic[28]:662 Asic[29]:662 Asic[30]:637 Asic[31]:662 Asic[32]:662
Asic[33]:662 Asic[34]:662 Asic[35]:662 Asic[36]:662 Asic[37]:662 Asic[38]:662 Asic[39]:662 Asic[40]:662
Asic[41]:662 Asic[42]:650 Asic[43]:662 Asic[44]:662 Asic[45]:662 Asic[46]:662 Asic[47]:662 Asic[48]:662
Asic[49]:662 Asic[50]:662 Asic[51]:662 Asic[52]:662 Asic[53]:662 Asic[54]:662 Asic[55]:650 Asic[56]:662
Asic[57]:650 Asic[58]:662 Asic[59]:662 Asic[60]:662 Asic[61]:662 Asic[62]:662
Chain:7 max freq=662
Chain:7 min freq=637
Miner fix freq ...
read PIC voltage=940 on chain[5]
Chain:5 chipnum=63
Chain[J6] voltage added=0.2V
Chain:5 temp offset=0
Chain:5 base freq=487
Asic[ 0]:618
Asic[ 1]:631 Asic[ 2]:650 Asic[ 3]:618 Asic[ 4]:631 Asic[ 5]:656 Asic[ 6]:618 Asic[ 7]:631 Asic[ 8]:656
Asic[ 9]:618 Asic[10]:631 Asic[11]:656 Asic[12]:631 Asic[13]:637 Asic[14]:606 Asic[15]:487 Asic[16]:637
Asic[17]:656 Asic[18]:618 Asic[19]:637 Asic[20]:656 Asic[21]:631 Asic[22]:650 Asic[23]:656 Asic[24]:631
Asic[25]:537 Asic[26]:656 Asic[27]:631 Asic[28]:587 Asic[29]:656 Asic[30]:612 Asic[31]:650 Asic[32]:656
Asic[33]:631 Asic[34]:650 Asic[35]:656 Asic[36]:631 Asic[37]:656 Asic[38]:656 Asic[39]:631 Asic[40]:656
Asic[41]:656 Asic[42]:543 Asic[43]:656 Asic[44]:656 Asic[45]:568 Asic[46]:656 Asic[47]:656 Asic[48]:631
Asic[49]:568 Asic[50]:656 Asic[51]:631 Asic[52]:625 Asic[53]:656 Asic[54]:631 Asic[55]:656 Asic[56]:656
Asic[57]:631 Asic[58]:656 Asic[59]:656 Asic[60]:631 Asic[61]:656 Asic[62]:656
Chain:5 max freq=656
Chain:5 min freq=487
read PIC voltage=940 on chain[6]
Chain:6 chipnum=63
Chain[J7] voltage added=0.1V
Chain:6 temp offset=0
Chain:6 base freq=687
Asic[ 0]:631
Asic[ 1]:631 Asic[ 2]:631 Asic[ 3]:631 Asic[ 4]:631 Asic[ 5]:631 Asic[ 6]:631 Asic[ 7]:631 Asic[ 8]:631
Asic[ 9]:631 Asic[10]:631 Asic[11]:631 Asic[12]:631 Asic[13]:631 Asic[14]:631 Asic[15]:631 Asic[16]:631
Asic[17]:631 Asic[18]:631 Asic[19]:631 Asic[20]:631 Asic[21]:631 Asic[22]:631 Asic[23]:631 Asic[24]:631
Asic[25]:631 Asic[26]:631 Asic[27]:631 Asic[28]:631 Asic[29]:631 Asic[30]:631 Asic[31]:631 Asic[32]:631
Asic[33]:631 Asic[34]:631 Asic[35]:637 Asic[36]:637 Asic[37]:637 Asic[38]:637 Asic[39]:637 Asic[40]:637
Asic[41]:637 Asic[42]:637 Asic[43]:637 Asic[44]:637 Asic[45]:637 Asic[46]:637 Asic[47]:637 Asic[48]:637
Asic[49]:637 Asic[50]:637 Asic[51]:637 Asic[52]:637 Asic[53]:637 Asic[54]:637 Asic[55]:637 Asic[56]:637
Asic[57]:637 Asic[58]:637 Asic[59]:637 Asic[60]:637 Asic[61]:637 Asic[62]:637
Chain:6 max freq=637
Chain:6 min freq=631
read PIC voltage=940 on chain[7]
Chain:7 chipnum=63
Chain[J8] voltage added=0.2V
Chain:7 temp offset=0
Chain:7 base freq=637
Asic[ 0]:637
Asic[ 1]:637 Asic[ 2]:637 Asic[ 3]:637 Asic[ 4]:637 Asic[ 5]:637 Asic[ 6]:637 Asic[ 7]:637 Asic[ 8]:637
Asic[ 9]:637 Asic[10]:637 Asic[11]:637 Asic[12]:637 Asic[13]:637 Asic[14]:637 Asic[15]:637 Asic[16]:637
Asic[17]:637 Asic[18]:637 Asic[19]:637 Asic[20]:637 Asic[21]:637 Asic[22]:637 Asic[23]:637 Asic[24]:637
Asic[25]:637 Asic[26]:637 Asic[27]:637 Asic[28]:637 Asic[29]:637 Asic[30]:637 Asic[31]:637 Asic[32]:637
Asic[33]:637 Asic[34]:637 Asic[35]:637 Asic[36]:637 Asic[37]:637 Asic[38]:637 Asic[39]:637 Asic[40]:637
Asic[41]:637 Asic[42]:637 Asic[43]:637 Asic[44]:637 Asic[45]:637 Asic[46]:637 Asic[47]:637 Asic[48]:637
Asic[49]:643 Asic[50]:643 Asic[51]:643 Asic[52]:643 Asic[53]:643 Asic[54]:643 Asic[55]:643 Asic[56]:643
Asic[57]:643 Asic[58]:643 Asic[59]:643 Asic[60]:643 Asic[61]:643 Asic[62]:643
Chain:7 max freq=643
Chain:7 min freq=637
max freq = 656
set baud=1
Chain[J6] PIC temp offset=62,0,0,0,0,0,35,28
chain[5] temp chip I2C addr=0x98
chain[5] has no middle temp, use special fix mode.
Chain[J6] chip[244] use PIC middle temp offset=0 typeID=55
New offset Chain[5] chip[244] local:26 remote:27 offset:29
Chain[J6] chip[244] get middle temp offset=29 typeID=55
Chain[J7] PIC temp offset=62,0,0,0,0,0,35,28
chain[6] temp chip I2C addr=0x98
chain[6] has no middle temp, use special fix mode.
Chain[J7] chip[244] use PIC middle temp offset=0 typeID=55
New offset Chain[6] chip[244] local:26 remote:27 offset:29
Chain[J7] chip[244] get middle temp offset=29 typeID=55
Chain[J8] PIC temp offset=62,0,0,0,0,0,35,28
chain[7] temp chip I2C addr=0x98
chain[7] has no middle temp, use special fix mode.
Chain[J8] chip[244] use PIC middle temp offset=0 typeID=55
New offset Chain[7] chip[244] local:26 remote:28 offset:28
Chain[J8] chip[244] get middle temp offset=28 typeID=55
miner rate=13501 voltage limit=900 on chain[5]
get PIC voltage=880 on chain[5], check: must be < 900
miner rate=13501 voltage limit=900 on chain[6]
get PIC voltage=900 on chain[6], check: must be < 900
miner rate=13501 voltage limit=900 on chain[7]
get PIC voltage=880 on chain[7], check: must be < 900
Chain[J6] set working voltage=880 [108]
Chain[J7] set working voltage=900 [74]
Chain[J8] set working voltage=880 [108]
do heat board 8xPatten for 1 times
start send works on chain[5]
start send works on chain[6]
start send works on chain[7]
get send work num :57456 on Chain[5]
get send work num :57456 on Chain[6]
get send work num :57456 on Chain[7]
wait recv nonce on chain[5]
wait recv nonce on chain[6]
wait recv nonce on chain[7]
get nonces on chain[5]
require nonce number:912
require validnonce number:57456
asic[00]=912 asic[01]=912 asic[02]=912 asic[03]=912 asic[04]=912 asic[05]=912 asic[06]=912 asic[07]=912
asic[08]=912 asic[09]=912 asic[10]=912 asic[11]=912 asic[12]=912 asic[13]=912 asic[14]=912 asic[15]=912
asic[16]=912 asic[17]=912 asic[18]=912 asic[19]=912 asic[20]=912 asic[21]=912 asic[22]=912 asic[23]=912
asic[24]=912 asic[25]=912 asic[26]=912 asic[27]=912 asic[28]=912 asic[29]=912 asic[30]=912 asic[31]=912
asic[32]=912 asic[33]=912 asic[34]=912 asic[35]=912 asic[36]=912 asic[37]=912 asic[38]=912 asic[39]=912
asic[40]=912 asic[41]=912 asic[42]=912 asic[43]=912 asic[44]=912 asic[45]=912 asic[46]=912 asic[47]=912
asic[48]=912 asic[49]=912 asic[50]=912 asic[51]=912 asic[52]=912 asic[53]=912 asic[54]=912 asic[55]=912
asic[56]=912 asic[57]=912 asic[58]=912 asic[59]=912 asic[60]=912 asic[61]=912 asic[62]=912
Below ASIC's core didn't receive all the nonce, they should receive 8 nonce each!
freq[00]=618 freq[01]=631 freq[02]=650 freq[03]=618 freq[04]=631 freq[05]=656 freq[06]=618 freq[07]=631
freq[08]=656 freq[09]=618 freq[10]=631 freq[11]=656 freq[12]=631 freq[13]=637 freq[14]=606 freq[15]=487
freq[16]=637 freq[17]=656 freq[18]=618 freq[19]=637 freq[20]=656 freq[21]=631 freq[22]=650 freq[23]=656
freq[24]=631 freq[25]=537 freq[26]=656 freq[27]=631 freq[28]=587 freq[29]=656 freq[30]=612 freq[31]=650
freq[32]=656 freq[33]=631 freq[34]=650 freq[35]=656 freq[36]=631 freq[37]=656 freq[38]=656 freq[39]=631
freq[40]=656 freq[41]=656 freq[42]=543 freq[43]=656 freq[44]=656 freq[45]=568 freq[46]=656 freq[47]=656
freq[48]=631 freq[49]=568 freq[50]=656 freq[51]=631 freq[52]=625 freq[53]=656 freq[54]=631 freq[55]=656
freq[56]=656 freq[57]=631 freq[58]=656 freq[59]=656 freq[60]=631 freq[61]=656 freq[62]=656
total valid nonce number:57456
total send work number:57456
require valid nonce number:57456
repeated_nonce_num:0
err_nonce_num:25912
last_nonce_num:14370
get nonces on chain[6]
require nonce number:912
require validnonce number:57456
asic[00]=912 asic[01]=912 asic[02]=912 asic[03]=912 asic[04]=912 asic[05]=912 asic[06]=912 asic[07]=912
asic[08]=912 asic[09]=912 asic[10]=912 asic[11]=912 asic[12]=912 asic[13]=912 asic[14]=912 asic[15]=912
asic[16]=912 asic[17]=912 asic[18]=912 asic[19]=912 asic[20]=912 asic[21]=912 asic[22]=912 asic[23]=912
asic[24]=912 asic[25]=912 asic[26]=912 asic[27]=912 asic[28]=912 asic[29]=912 asic[30]=912 asic[31]=912
asic[32]=912 asic[33]=912 asic[34]=912 asic[35]=912 asic[36]=912 asic[37]=912 asic[38]=912 asic[39]=912
asic[40]=912 asic[41]=912 asic[42]=912 asic[43]=912 asic[44]=912 asic[45]=912 asic[46]=912 asic[47]=912
asic[48]=912 asic[49]=912 asic[50]=912 asic[51]=912 asic[52]=912 asic[53]=912 asic[54]=912 asic[55]=912
asic[56]=912 asic[57]=912 asic[58]=912 asic[59]=912 asic[60]=912 asic[61]=912 asic[62]=912
Below ASIC's core didn't receive all the nonce, they should receive 8 nonce each!
freq[00]=631 freq[01]=631 freq[02]=631 freq[03]=631 freq[04]=631 freq[05]=631 freq[06]=631 freq[07]=631
freq[08]=631 freq[09]=631 freq[10]=631 freq[11]=631 freq[12]=631 freq[13]=631 freq[14]=631 freq[15]=631
freq[16]=631 freq[17]=631 freq[18]=631 freq[19]=631 freq[20]=631 freq[21]=631 freq[22]=631 freq[23]=631
freq[24]=631 freq[25]=631 freq[26]=631 freq[27]=631 freq[28]=631 freq[29]=631 freq[30]=631 freq[31]=631
freq[32]=631 freq[33]=631 freq[34]=631 freq[35]=637 freq[36]=637 freq[37]=637 freq[38]=637 freq[39]=637
freq[40]=637 freq[41]=637 freq[42]=637 freq[43]=637 freq[44]=637 freq[45]=637 freq[46]=637 freq[47]=637
freq[48]=637 freq[49]=637 freq[50]=637 freq[51]=637 freq[52]=637 freq[53]=637 freq[54]=637 freq[55]=637
freq[56]=637 freq[57]=637 freq[58]=637 freq[59]=637 freq[60]=637 freq[61]=637 freq[62]=637
total valid nonce number:57456
total send work number:57456
require valid nonce number:57456
repeated_nonce_num:0
err_nonce_num:25987
last_nonce_num:14368
get nonces on chain[7]
require nonce number:912
require validnonce number:57456
asic[00]=912 asic[01]=912 asic[02]=912 asic[03]=912 asic[04]=912 asic[05]=912 asic[06]=912 asic[07]=912
asic[08]=907 asic[09]=912 asic[10]=912 asic[11]=912 asic[12]=912 asic[13]=912 asic[14]=912 asic[15]=912
asic[16]=912 asic[17]=912 asic[18]=912 asic[19]=909 asic[20]=912 asic[21]=912 asic[22]=912 asic[23]=912
asic[24]=912 asic[25]=912 asic[26]=912 asic[27]=912 asic[28]=912 asic[29]=912 asic[30]=912 asic[31]=912
asic[32]=912 asic[33]=912 asic[34]=912 asic[35]=912 asic[36]=912 asic[37]=912 asic[38]=912 asic[39]=912
asic[40]=912 asic[41]=912 asic[42]=912 asic[43]=912 asic[44]=912 asic[45]=912 asic[46]=912 asic[47]=912
asic[48]=912 asic[49]=912 asic[50]=912 asic[51]=912 asic[52]=912 asic[53]=912 asic[54]=912 asic[55]=911
asic[56]=912 asic[57]=912 asic[58]=912 asic[59]=912 asic[60]=912 asic[61]=912 asic[62]=912
Below ASIC's core didn't receive all the nonce, they should receive 8 nonce each!
asic[08]=907
core[049]=7 core[053]=5 core[056]=7
asic[19]=909
core[064]=7 core[112]=6
asic[55]=911
core[007]=7
freq[00]=637 freq[01]=637 freq[02]=637 freq[03]=637 freq[04]=637 freq[05]=637 freq[06]=637 freq[07]=637
freq[08]=637 freq[09]=637 freq[10]=637 freq[11]=637 freq[12]=637 freq[13]=637 freq[14]=637 freq[15]=637
freq[16]=637 freq[17]=637 freq[18]=637 freq[19]=637 freq[20]=637 freq[21]=637 freq[22]=637 freq[23]=637
freq[24]=637 freq[25]=637 freq[26]=637 freq[27]=637 freq[28]=637 freq[29]=637 freq[30]=637 freq[31]=637
freq[32]=637 freq[33]=637 freq[34]=637 freq[35]=637 freq[36]=637 freq[37]=637 freq[38]=637 freq[39]=637
freq[40]=637 freq[41]=637 freq[42]=637 freq[43]=637 freq[44]=637 freq[45]=637 freq[46]=637 freq[47]=637
freq[48]=637 freq[49]=643 freq[50]=643 freq[51]=643 freq[52]=643 freq[53]=643 freq[54]=643 freq[55]=643
freq[56]=643 freq[57]=643 freq[58]=643 freq[59]=643 freq[60]=643 freq[61]=643 freq[62]=643
total valid nonce number:57447
total send work number:57456
require valid nonce number:57456
repeated_nonce_num:0
err_nonce_num:26183
last_nonce_num:35748
chain[5]: All chip cores are opened OK!
Test Patten on chain[5]: OK!
chain[6]: All chip cores are opened OK!
Test Patten on chain[6]: OK!
chain[7]: All chip cores are opened OK!
Test Patten on chain[7]: OK!
setStartTimePoint total_tv_start_sys=217 total_tv_end_sys=218
restartNum = 2 , auto-reinit enabled...
do read_temp_func once...
do check_asic_reg 0x08
get RT hashrate from Chain[5]: (asic index start from 1-63)
Asic[01]=72.5110 Asic[02]=68.6020 Asic[03]=74.4230 Asic[04]=74.6750 Asic[05]=71.4540 Asic[06]=77.5610 Asic[07]=74.7760 Asic[08]=74.3900
Asic[09]=77.7790 Asic[10]=76.7220 Asic[11]=73.8020 Asic[12]=68.5850 Asic[13]=76.1680 Asic[14]=72.4770 Asic[15]=73.0470 Asic[16]=57.8810
Asic[17]=74.4740 Asic[18]=76.4530 Asic[19]=67.8800 Asic[20]=70.1280 Asic[21]=73.7520 Asic[22]=74.6580 Asic[23]=73.6850 Asic[24]=78.5170
Asic[25]=73.6850 Asic[26]=63.6860 Asic[27]=80.9660 Asic[28]=73.9200 Asic[29]=68.9870 Asic[30]=75.6310 Asic[31]=74.9770 Asic[32]=69.4570
Asic[33]=74.6580 Asic[34]=79.8930 Asic[35]=76.6710 Asic[36]=74.3730 Asic[37]=66.6050 Asic[38]=76.7380 Asic[39]=71.4540 Asic[40]=69.3060
Asic[41]=72.5610 Asic[42]=73.8530 Asic[43]=58.9210 Asic[44]=75.3800 Asic[45]=73.1310 Asic[46]=68.4000 Asic[47]=77.6780 Asic[48]=73.1150
Asic[49]=69.2890 Asic[50]=62.8130 Asic[51]=74.2720 Asic[52]=73.1480 Asic[53]=67.4440 Asic[54]=72.4940 Asic[55]=68.1990 Asic[56]=72.4100
Asic[57]=75.3460 Asic[58]=66.1350 Asic[59]=72.9800 Asic[60]=78.1480 Asic[61]=72.3260 Asic[62]=72.5610 Asic[63]=77.7950
get RT hashrate from Chain[6]: (asic index start from 1-63)
Asic[01]=67.6620 Asic[02]=75.9840 Asic[03]=70.3300 Asic[04]=75.5640 Asic[05]=62.8470 Asic[06]=70.2790 Asic[07]=74.5240 Asic[08]=72.9130
Asic[09]=70.6320 Asic[10]=72.5610 Asic[11]=73.9370 Asic[12]=77.3420 Asic[13]=72.4440 Asic[14]=68.8030 Asic[15]=73.0810 Asic[16]=73.8360
Asic[17]=73.5510 Asic[18]=73.9700 Asic[19]=71.0340 Asic[20]=71.1680 Asic[21]=72.1580 Asic[22]=78.8190 Asic[23]=71.9230 Asic[24]=69.4570
Asic[25]=67.7630 Asic[26]=71.7220 Asic[27]=76.4030 Asic[28]=71.1180 Asic[29]=68.7360 Asic[30]=69.7090 Asic[31]=77.5610 Asic[32]=70.1790
Asic[33]=67.9140 Asic[34]=72.3930 Asic[35]=64.5920 Asic[36]=72.1920 Asic[37]=74.6080 Asic[38]=75.4470 Asic[39]=73.8700 Asic[40]=73.9370
Asic[41]=66.2860 Asic[42]=79.4230 Asic[43]=75.8160 Asic[44]=68.6350 Asic[45]=74.7920 Asic[46]=70.7990 Asic[47]=71.2360 Asic[48]=73.8700
Asic[49]=66.5380 Asic[50]=70.6150 Asic[51]=72.6280 Asic[52]=75.7490 Asic[53]=71.8400 Asic[54]=76.5370 Asic[55]=73.5340 Asic[56]=69.2390
Asic[57]=75.1280 Asic[58]=74.3230 Asic[59]=73.4330 Asic[60]=72.3430 Asic[61]=77.6780 Asic[62]=82.4600 Asic[63]=69.5240
get RT hashrate from Chain[7]: (asic index start from 1-63)
Asic[01]=73.5510 Asic[02]=75.9160 Asic[03]=80.1110 Asic[04]=76.9900 Asic[05]=76.1510 Asic[06]=73.5170 Asic[07]=74.9940 Asic[08]=73.1150
Asic[09]=70.6650 Asic[10]=70.6990 Asic[11]=72.4770 Asic[12]=70.1450 Asic[13]=74.3060 Asic[14]=71.8060 Asic[15]=74.7420 Asic[16]=75.6650
Asic[17]=76.8220 Asic[18]=69.5240 Asic[19]=72.0910 Asic[20]=75.2620 Asic[21]=72.0240 Asic[22]=73.2660 Asic[23]=76.2690 Asic[24]=69.9440
Asic[25]=67.7290 Asic[26]=71.7050 Asic[27]=74.6250 Asic[28]=78.2320 Asic[29]=69.8430 Asic[30]=68.4670 Asic[31]=71.5210 Asic[32]=68.9540
Asic[33]=74.6250 Asic[34]=71.8730 Asic[35]=74.4400 Asic[36]=74.8760 Asic[37]=73.9030 Asic[38]=72.9300 Asic[39]=69.6250 Asic[40]=74.9430
Asic[41]=72.7620 Asic[42]=69.4910 Asic[43]=67.4270 Asic[44]=71.4870 Asic[45]=74.4570 Asic[46]=66.6550 Asic[47]=67.5450 Asic[48]=75.4800
Asic[49]=72.2590 Asic[50]=72.9300 Asic[51]=75.6820 Asic[52]=71.9070 Asic[53]=67.9640 Asic[54]=67.8470 Asic[55]=74.3900 Asic[56]=71.0010
Asic[57]=75.8490 Asic[58]=74.9270 Asic[59]=72.3930 Asic[60]=74.3730 Asic[61]=75.5310 Asic[62]=73.8190 Asic[63]=72.4440
Check Chain[J6] ASIC RT error: (asic index start from 1-63)
Check Chain[J7] ASIC RT error: (asic index start from 1-63)
Check Chain[J8] ASIC RT error: (asic index start from 1-63)
Done check_asic_reg
do read temp on Chain[5]
Chain[5] Chip[62] TempTypeID=55 middle offset=29
Chain[5] Chip[62] local Temp=60
Chain[5] Chip[62] middle Temp=70
Special fix Chain[5] Chip[62] middle Temp = 75
Done read temp on Chain[5]
do read temp on Chain[6]
Chain[6] Chip[62] TempTypeID=55 middle offset=29
Chain[6] Chip[62] local Temp=60
Chain[6] Chip[62] middle Temp=72
Special fix Chain[6] Chip[62] middle Temp = 75
Done read temp on Chain[6]
do read temp on Chain[7]
Chain[7] Chip[62] TempTypeID=55 middle offset=28
Chain[7] Chip[62] local Temp=62
Chain[7] Chip[62] middle Temp=72
Special fix Chain[7] Chip[62] middle Temp = 77
Done read temp on Chain[7]
set FAN speed according to: temp_highest=62 temp_top1[PWM_T]=62 temp_top1[TEMP_POS_LOCAL]=62 temp_change=0 fix_fan_steps=0
FAN PWM: 74
read_temp_func Done!
CRC error counter=0
submitted by Timsierramist to BITMAIN [link] [comments]

FPGA based Bitcoin Miner ELE 432- FPGA Bitcoin Miner Bitcoin Mining with FPGAs (EC551 Final Project) BitCoin FPGA Demo Liquid Cooling Eight FPGA Boards with Xilinx VU13P

Open Source FGPA Bitcoin MinerJust released was the Open Source FPGA Bitcoin Miner software. This miner allows bitcoins to be mined using a commercially available FPGA board. FPGA boards consume much less electricity compared to GPUs for the hashing work performed when mining bitcoins. A miner that makes use of a compatible FPGA Board. The miner works either in a mining pool or solo.. This is the first open source FPGA Bitcoin miner. It was released on May 20, 2011. FPGA Bitcoin Mining. At the foundation of block creation and mining is the calculation of this digital signature. Different cryptocurrencies use different approaches to generate the signature. For the most popular cryptocurrency, Bitcoin, the signature is calculated using a cryptographic hashing function. Programable And Upgradable FPGA Chips. Easy to service hashing boards for longer mining life. Quieter miners. Less noise pollution. Order Now New SHA256 Bitcoin Miner is Here! Veden is on a mission to help keep Bitcoin decentralized. Like a lot of my fellow miners out there, I came from a GPU mining world. As a GPU miner myself, I was both curious and concerned about the growing FPGA mining ecosystem. After weeks of research and testing, we compiled the first version of the FPGA.guide to share what we've learned so far. This is now the fourth revision of FPGA.guide.

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FPGA based Bitcoin Miner

This is the video showing the final project of EC551 in Spring semester,2015. This project, Bitcoin mining, is done by group "Bitminers". The group members are: Tony Ye, Marcia Sahaya Louis, Alan ... FPGA Miner for Cryptocurrency Mining: Why Use FPGA for Mining? FPGA vs GPU vs ASIC Explained - Duration: 7:56. FPGA Guide 626 views Watch us stress-test eight BittWare XUPVV4 FPGA boards featuring the Xilinx VU13P with liquid cooling! We are soon to release the even more powerful XUPVVP (300 amp) version of this board with ... Bitcoin Mining with FPGAs (EC551 Final Project) - Duration: 6:11. Advanced Digital Design with Verilog and FPGAs - Boston University 5,295 views Ben Heck's FPGA Dev Board Tutorial - Duration: 24:52. element14 presents 183,874 views. ... T4D #84 - Pt 2 Bitcoin Mining, BFL ASIC vs FPGA vs GPU vs CPU - Duration: 28:50. mjlorton 63,615 views.

http://forex-indonesia.eccenchicknus.tk